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| The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7709S Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series Rev.5.00 2003.9.18 Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7709S Group Hardware Manual REJ09B0081-0500O Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 5.00, 09/03, page iv of xliv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 5.00, 09/03, page v of xliv Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 5.00, 09/03, page vi of xliv Preface This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions necessary for configuring a user system. This LSI is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timer, three serial communication interfaces, realtime clock (RTC), use break controller (UBC), bus state controller (BSC) and I/O ports. This LSI can be used as a microcomputer for devices that require both high speed and low power consumption. Target Readers: This manual is designed for use by people who design application systems using the SH7709S. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7709S. The SH3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual. How to Use the Book: * To understand general functions Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. * To understanding CPU functions Refer to the separate SH3, SH-3E, SH3-DSP Programming Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/eng/) * User manuals for SH7709S Name of Document SH7709S Group Hardware Manual SH3, SH-3E, SH3-DSP Programming Manual Document No. This manual ADE-602-156 Rev. 5.00, 09/03, page vii of xliv * User manuals for development tools Name of Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Simulator/Debugger User's Manual Embedded Workshop User's Manual Document No. ADE-702-246 ADE-702-186 ADE-702-201 Rev. 5.00, 09/03, page viii of xliv List of Items Revised or Added for This Version Section Page 6 Description 1.2 Block Diagram Figure 1.1 Block Diagram ASERAM deleted from figure BRIDGE UDI INTC CPG/WDT External bus interface ASERAM deleted from legend 2.5.1 Processor States 53 Description amended In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of on-chip supporting modules other than the bus state controller (BSC) are Refer to initialized. the register configurations in the relevant sections for further details. 5.4 Memory-Mapped Cache 5.4.1 Address Array 113 Description amended This operation is used to invalidate the address specification for a cache. Write back will take place when the U bit of the entry that received a hit is 1. Note that, when a 0 is written to the V bit, a 0 should always be written to the U bit of the same entry, too. I bus 2 Rev. 5.0, 09/03, page ix of xliv Section Page 115, 116 Description 5.4.3 Examples of Usage (1) Invalidating a Specific Entry Description amended A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry's U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to. In the following example, the write data is specified in R0 and the address is specified in R1. ; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0 ; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0 ; MOV.L R0, @R1 To invalidate all entries and ways, write 0 to the following addresses. Addresses F000 0000 F000 0010 F000 0020 : F000 3FF0 This involves a total of 1,024 writes. The above operation should be performed using a non-cacheable area. (2) Invalidating a Specific Address Newly added (3) Reading Data from a Specific Entry Description amended ; R0 = H'F100 004C; Data array access, Entry = H'04, ; Way = 0, Longword address = 3 ; MOV.L R0, @R1 ; Longword 3 is read. 6.2.6 Interrupt 127 Exception Handling and Priority Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) 6.3.6 Interrupt Request Register 0 (IRR0) 138 IPR (bit numbers) for SCI amended (Before)IPRB(3-0) (After)IPRB(7-4) Description amended When clearing an IRQ5R-IRQ0R bit to 0, read the bit while bit set to 1, and then write 0. In this case, 0 should be written only to the bits to be cleared and 1 to the other bits. The contents of the bits to which 1 is written do not change. Description added Bit 1--Module Standby 1 (MSTP1) Before switching the RTC to module standby, access at least one among the registers RTC, SCI, and TMU. 8.2.1 Standby Control 184 Register (STBCR) Rev. 5.0, 09/03, page x of xliv Section Page 187 Description 8.3.3 Precautions when Using the Sleep Mode 8.5.1 Transition to Module Standby Function Newley added 191 Note *3 added to bit table Note: 3. Before putting the RTC into module standby status, first access one or more of the RTC, SCI, and TMU registers. The RTC may then be put into module standby status. 9.3 Clock Operating Modes Table 9.4 Available Combinations of Clock Mode and FRQCR Values 9.5.1 Changing the Multiplication Rate 210 2. under cautions amended The peripheral clock frequency should not be set higher than the frequency of the CKIO pin, higher than 33.34 MHz. 213 Description added 5.Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. * Bits IFC2 to IFC0 are changed. * STC2 to STC0 are not changed. * The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. 9.8.2 Changing the Frequency 218, 219 Description added 5.The counter stops at a value of H'00 or H'01. The stop value depends on the clock ratio. When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. * Bits IFC2 to IFC0 are changed. * STC2 to STC0 are not changed. * The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. 10.1.1 Features 10.2.5 Individual Memory Control Register (MCR) 223 246 Refresh function description deleted Description added Bit 7--Synchronous DRAM Bank Active (RASD): Specifies whether synchronous DRAM is used in bank active mode or autoprecharge mode. Set auto-precharge mode when areas 2 and 3 are both designated as synchronous DRAM space. The bank active mode should not be used unless the bus width for all areas is 32 bits. Rev. 5.0, 09/03, page xi of xliv Section Page Description 10.2.13 MCS0 Control 258 Register (MCSCR0) Description added Bit 6--CS2/CS0 Select (CS2/0) Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7. Bank Active description added ... .In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. The bank active mode should not be used unless the bus width for all areas is 32 bits. 10.3.4 Synchronous DRAM Interface 290 10.3.6 PCMCIA Interface Figure 10.32 Basic Timing for PCMCIA Memory Card Interface 310 Figure amended D15 to D0 (Write) Figure amended T1 CKIO A25 to A0 T2 Twait T1 T2 Twait T1 T2 10.3.7 Waits between 320 Access Cycles Figure 10.40 Waits between Access Cycles 10.3.10 MCS[0] to MCS[7] Pin Control 323 Description amended This enables 32-, 64-, 128-, or 256-Mbit memory to be connected to area 0 or area 2. However, only CS2/0 = 0 (area 0) should be used for MCSCR0. Table 10.15 shows MCSCR0-MCSCR7 settings and MCS[0]-MCS[7] assertion conditions. 11.6 Usage Notes 387 Description added 13. DMAC transfers should not be performed in the sleep mode under conditions other than when the clock ratio of I (onchip clock) to B (bus clock) is 1:1. 14. When the following three conditions are all met, the frequency control register (FRQCR) should not be changed while a DMAC transfer is in progress. * Bits IFC2 to IFC0 are changed. * STC2 to STC0 in FRQCR are not changed. * The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. 13.4.3 Precautions when Using RTC Module Standby 426 Newly added Rev. 5.0, 09/03, page xii of xliv Section Page 550 Description 16.4 SCIF Interrupts Description amended When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. When data exceeding the transmit trigger number is written to the transmit data register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it. When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed when the RDF flag in SCSSR is set to 1. When receive data less than the receive trigger number is read from the receive data register (SCFRDR) by the DMAC, 1 is read from the RDF flag, after which 0 is written to it to clear it. 16.5 Usage Notes 551 Description amended 1. SCFTDR Writing and TDFE Flag: However, if the number of data bytes written to SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again even after having been cleared to 0. TDFE clearing should therefore be carried out after data exceeding the specified transmit trigger number has been written to SCFTDR. 2. SCFRDR Reading and RDF Flag: However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again even after having been cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. 19.13.2 SC Port Data Register (SCPDR) 610 Title Amended Rev. 5.0, 09/03, page xiii of xliv Section Page 622 Description 20.3 Bus Master Interface Figure 20.2 A/D Data Register Access Operation (Reading H'AA40) Figure amended Upper byte read CPU receives data H'AA Module internal data bus Bus interface TEMP [H'40] ADDRn H [H'AA] Lower byte read CPU receives data H'40 ADDRn L [H'40] n = A to D Bus interface Module internal data bus TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] n = A to D 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings 657 Caution added 2.Until voltage is applied to all power supplies, a low level is input at the RESETP pin, and CKIO has operated for a maximum of 4 clock cycles, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. Note that the RESETP pin cannot receive a low level signal while a low level signal is being input to the CA pin. 23.2 DC Characteristics Table 23.2 DC Characteristics 659, 662 Test conditions for in sleep mode amended Item Symbol Min -- -- Typ Max 15 10 30 20 Unit Test Conditions * : When there is no other external bus cycle other than the refresh cycle. Vcc = 1.9 V VccQ = 3.3 V B = 33MHz Note * added * If the IRL and IRLS interrupts are used, the minimum is 1.9 V. 1 Sleep Icc 1 mode* IccQ Rev. 5.0, 09/03, page xiv of xliv Section Page 690 Description 23.3.6 Synchronous DRAM Timing Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2) Tnop cycle deleted from figure Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tRDS2 tRDH2 tDQMD tCASD2 tRWD Row address tAD tAD Read command tAD Column address tCSD3 CKE (High) tDAKD1 tDAKD1 DACKn Rev. 5.0, 09/03, page xv of xliv Section Page Description A.2 Pin Specifications 723 Table A.2 Pin Specifications Function information amended for VCC-RTC, VCC-PLL1, VCC- PLL2, and VCC Pin Pin No. (FP-208C, FP-208E) Pin No. (BP240A) E2 I/O Function VCC- 3 RTC VCC- 145 PLL1 150 VCC- PLL2 VCC 29, 81, 134, 154, 175 Power supply Power supply RTC oscillator power supply (2.0/1.9/1.8/1.7 V) PLL power supply (2.0/1.9/1.8/1.7 V) F16, E17 L3, L4, U11, T11, J17, J16, E18, C19, C12, D12 Power supply Internal power supply (2.0/1.9/1.8/1.7 V) A.3 Treatment of Unused Pins A.4 Pin States in Access to Each Address Space Table A.3 Pin States (Ordinary Memory/Little Endian) Table A.4 Pin States (Ordinary Memory/Big Endian) Table A.5 Pin States (Burst ROM/Little Endian) Table A.6 Pin States (Burst ROM/Big Endian) Table A.9 Pin States (PCMCIA/Little Endian) Table A.10 Pin States (PCMCIA/Big Endian) 724 "When RTC is not used" and "When PLL2 is not used" amended (Before) (1.9/1.8V) (After) (2.0/1.9/1.8/1.7V) Note 2 amended Note: 2. Unused data pins should be switched to the port function, or pulled up. 726 to 738 Rev. 5.0, 09/03, page xvi of xliv Contents Section 1 Overview and Pin Functions.......................................................................... 1.1 1.2 1.3 SH7709S Features ............................................................................................................. Block Diagram .................................................................................................................. Pin Description .................................................................................................................. 1.3.1 Pin Assignment .................................................................................................... 1.3.2 Pin Function ......................................................................................................... 1 1 6 7 7 9 Section 2 CPU....................................................................................................................... 19 2.1 Register Configuration ...................................................................................................... 2.1.1 Privileged Mode and Banks.................................................................................. 2.1.2 General Registers ................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Control Registers.................................................................................................. Data Formats ..................................................................................................................... 2.2.1 Data Format in Registers ...................................................................................... 2.2.2 Data Format in Memory ....................................................................................... Instruction Features ........................................................................................................... 2.3.1 Execution Environment ........................................................................................ 2.3.2 Addressing Modes................................................................................................ 2.3.3 Instruction Formats............................................................................................... Instruction Set.................................................................................................................... 2.4.1 Instruction Set Classified by Function.................................................................. 2.4.2 Instruction Code Map ........................................................................................... Processor States and Processor Modes.............................................................................. 2.5.1 Processor States.................................................................................................... 2.5.2 Processor Modes .................................................................................................. 19 19 22 23 23 25 25 25 26 26 28 32 35 35 50 53 53 54 2.2 2.3 2.4 2.5 Section 3 Memory Management Unit (MMU)............................................................ 55 3.1 Overview ........................................................................................................................... 3.1.1 Features ................................................................................................................ 3.1.2 Role of MMU ....................................................................................................... 3.1.3 SH7709S MMU.................................................................................................... 3.1.4 Register Configuration ......................................................................................... Register Description .......................................................................................................... TLB Functions................................................................................................................... 3.3.1 Configuration of the TLB ..................................................................................... 3.3.2 TLB Indexing ....................................................................................................... 3.3.3 TLB Address Comparison.................................................................................... 3.3.4 Page Management Information ............................................................................ 55 55 55 58 61 61 63 63 65 66 68 3.2 3.3 Rev. 5.00, 09/03, page xvii of xliv 3.4 3.5 3.6 3.7 MMU Functions ................................................................................................................ 3.4.1 MMU Hardware Management ............................................................................. 3.4.2 MMU Software Management............................................................................... 3.4.3 MMU Instruction (LDTLB) ................................................................................. 3.4.4 Avoiding Synonym Problems............................................................................... MMU Exceptions .............................................................................................................. 3.5.1 TLB Miss Exception ............................................................................................ 3.5.2 TLB Protection Violation Exception.................................................................... 3.5.3 TLB Invalid Exception......................................................................................... 3.5.4 Initial Page Write Exception ................................................................................ 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) ................................................................................................ Configuration of Memory-Mapped TLB........................................................................... 3.6.1 Address Array ...................................................................................................... 3.6.2 Data Array ............................................................................................................ 3.6.3 Usage Examples ................................................................................................... Usage Note ........................................................................................................................ 69 69 69 70 72 74 74 75 76 77 79 80 80 81 83 83 Section 4 Exception Handling.......................................................................................... 85 4.1 Overview ........................................................................................................................... 85 4.1.1 Features ................................................................................................................ 85 4.1.2 Register Configuration ......................................................................................... 85 Exception Handling Function............................................................................................ 85 4.2.1 Exception Handling Flow..................................................................................... 85 4.2.2 Exception Vector Addresses................................................................................. 86 4.2.3 Acceptance of Exceptions .................................................................................... 88 4.2.4 Exception Codes................................................................................................... 90 4.2.5 Exception Request Masks .................................................................................... 91 4.2.6 Returning from Exception Handling .................................................................... 91 Register Descriptions......................................................................................................... 92 Exception Handling Operation .......................................................................................... 93 4.4.1 Reset..................................................................................................................... 93 4.4.2 Interrupts .............................................................................................................. 93 4.4.3 General Exceptions............................................................................................... 94 Individual Exception Operations ....................................................................................... 94 4.5.1 Resets ................................................................................................................... 94 4.5.2 General Exceptions............................................................................................... 95 4.5.3 Interrupts .............................................................................................................. 99 Cautions............................................................................................................................. 100 4.2 4.3 4.4 4.5 4.6 Section 5 Cache .................................................................................................................... 103 5.1 Overview ........................................................................................................................... 103 5.1.1 Features ................................................................................................................ 103 Rev. 5.00, 09/03, page xviii of xliv 5.2 5.3 5.4 5.1.2 Cache Structure .................................................................................................... 103 5.1.3 Register Configuration ......................................................................................... 105 Register Description .......................................................................................................... 105 5.2.1 Cache Control Register (CCR) ............................................................................. 105 5.2.2 Cache Control Register 2 (CCR2) ........................................................................ 106 Cache Operation ................................................................................................................ 109 5.3.1 Searching the Cache ............................................................................................. 109 5.3.2 Read Access ......................................................................................................... 111 5.3.3 Prefetch Operation................................................................................................ 111 5.3.4 Write Access ........................................................................................................ 111 5.3.5 Write-Back Buffer................................................................................................ 111 5.3.6 Coherency of Cache and External Memory.......................................................... 112 Memory-Mapped Cache.................................................................................................... 112 5.4.1 Address Array ...................................................................................................... 112 5.4.2 Data Array ............................................................................................................ 113 5.4.3 Examples of Usage ............................................................................................... 115 Section 6 Interrupt Controller (INTC) ........................................................................... 117 6.1 Overview ........................................................................................................................... 117 6.1.1 Features ................................................................................................................ 117 6.1.2 Block Diagram ..................................................................................................... 118 6.1.3 Pin Configuration ................................................................................................. 119 6.1.4 Register Configuration ......................................................................................... 120 Interrupt Sources ............................................................................................................... 121 6.2.1 NMI Interrupt ....................................................................................................... 121 6.2.2 IRQ Interrupts ...................................................................................................... 121 6.2.3 IRL Interrupts....................................................................................................... 122 6.2.4 PINT Interrupts .................................................................................................... 124 6.2.5 On-Chip Peripheral Module Interrupts................................................................. 124 6.2.6 Interrupt Exception Handling and Priority ........................................................... 125 INTC Registers.................................................................................................................. 131 6.3.1 Interrupt Priority Registers A to E (IPRA-IPRE) ................................................ 131 6.3.2 Interrupt Control Register 0 (ICR0) ..................................................................... 132 6.3.3 Interrupt Control Register 1 (ICR1) ..................................................................... 133 6.3.4 Interrupt Control Register 2 (ICR2) ..................................................................... 136 6.3.5 PINT Interrupt Enable Register (PINTER) .......................................................... 137 6.3.6 Interrupt Request Register 0 (IRR0)..................................................................... 138 6.3.7 Interrupt Request Register 1 (IRR1)..................................................................... 140 6.3.8 Interrupt Request Register 2 (IRR2)..................................................................... 141 INTC Operation................................................................................................................. 143 6.4.1 Interrupt Sequence................................................................................................ 143 6.4.2 Multiple Interrupts................................................................................................ 145 Interrupt Response Time ................................................................................................... 145 Rev. 5.00, 09/03, page xix of xliv 6.2 6.3 6.4 6.5 Section 7 User Break Controller...................................................................................... 149 7.1 Overview ........................................................................................................................... 149 7.1.1 Features ................................................................................................................ 149 7.1.2 Block Diagram ..................................................................................................... 150 7.1.3 Register Configuration ......................................................................................... 151 Register Descriptions......................................................................................................... 152 7.2.1 Break Address Register A (BARA)...................................................................... 152 7.2.2 Break Address Mask Register A (BAMRA) ........................................................ 153 7.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 154 7.2.4 Break Address Register B (BARB) ...................................................................... 156 7.2.5 Break Address Mask Register B (BAMRB)......................................................... 157 7.2.6 Break Data Register B (BDRB) ........................................................................... 158 7.2.7 Break Data Mask Register B (BDMRB) .............................................................. 159 7.2.8 Break Bus Cycle Register B (BBRB)................................................................... 160 7.2.9 Break Control Register (BRCR)........................................................................... 162 7.2.10 Execution Times Break Register (BETR) ............................................................ 166 7.2.11 Branch Source Register (BRSR) .......................................................................... 167 7.2.12 Branch Destination Register (BRDR) .................................................................. 168 7.2.13 Break ASID Register A (BASRA) ....................................................................... 169 7.2.14 Break ASID Register B (BASRB) ....................................................................... 169 Operation Description ....................................................................................................... 170 7.3.1 Flow of the User Break Operation........................................................................ 170 7.3.2 Break on Instruction Fetch Cycle ......................................................................... 170 7.3.3 Break by Data Access Cycle ................................................................................ 171 7.3.4 Sequential Break .................................................................................................. 172 7.3.5 Value of Saved Program Counter......................................................................... 172 7.3.6 PC Trace............................................................................................................... 173 7.3.7 Usage Examples ................................................................................................... 174 7.3.8 Notes .................................................................................................................... 179 7.2 7.3 Section 8 Power-Down Modes......................................................................................... 181 8.1 Overview ........................................................................................................................... 181 8.1.1 Power-Down Modes............................................................................................. 181 8.1.2 Pin Configuration ................................................................................................. 183 8.1.3 Register Configuration ......................................................................................... 183 Register Descriptions......................................................................................................... 183 8.2.1 Standby Control Register (STBCR) ..................................................................... 183 8.2.2 Standby Control Register 2 (STBCR2) ................................................................ 185 Sleep Mode........................................................................................................................ 187 8.3.1 Transition to Sleep Mode ..................................................................................... 187 8.3.2 Canceling Sleep Mode.......................................................................................... 187 8.3.3 Precautions when Using the Sleep Mode ............................................................. 187 Standby Mode.................................................................................................................... 188 8.2 8.3 8.4 Rev. 5.00, 09/03, page xx of xliv 8.5 8.6 8.7 8.4.1 Transition to Standby Mode ................................................................................. 188 8.4.2 Canceling Standby Mode ..................................................................................... 189 8.4.3 Clock Pause Function........................................................................................... 190 Module Standby Function ................................................................................................. 191 8.5.1 Transition to Module Standby Function............................................................... 191 8.5.2 Clearing Module Standby Function...................................................................... 191 Timing of STATUS Pin Changes ...................................................................................... 192 8.6.1 Timing for Resets ................................................................................................. 192 8.6.2 Timing for Canceling Standby ............................................................................. 194 8.6.3 Timing for Canceling Sleep Mode ....................................................................... 196 Hardware Standby Mode................................................................................................... 199 8.7.1 Transition to Hardware Standby Mode ................................................................ 199 8.7.2 Canceling Hardware Standby Mode..................................................................... 199 8.7.3 Hardware Standby Mode Timing ......................................................................... 200 Section 9 On-Chip Oscillation Circuits ......................................................................... 203 9.1 9.2 Overview ........................................................................................................................... 203 9.1.1 Features ................................................................................................................ 203 Overview of CPG .............................................................................................................. 204 9.2.1 CPG Block Diagram............................................................................................. 204 9.2.2 CPG Pin Configuration ........................................................................................ 206 9.2.3 CPG Register Configuration................................................................................. 206 Clock Operating Modes..................................................................................................... 207 Register Descriptions......................................................................................................... 211 9.4.1 Frequency Control Register (FRQCR) ................................................................. 211 Changing the Frequency.................................................................................................... 213 9.5.1 Changing the Multiplication Rate ........................................................................ 213 9.5.2 Changing the Division Ratio ................................................................................ 213 Overview of WDT............................................................................................................. 214 9.6.1 Block Diagram of WDT ....................................................................................... 214 9.6.2 Register Configuration ......................................................................................... 214 WDT Registers .................................................................................................................. 215 9.7.1 Watchdog Timer Counter (WTCNT) ................................................................... 215 9.7.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 215 9.7.3 Notes on Register Access ..................................................................................... 217 Using the WDT ................................................................................................................. 218 9.8.1 Canceling Standby................................................................................................ 218 9.8.2 Changing the Frequency....................................................................................... 218 9.8.3 Using Watchdog Timer Mode .............................................................................. 219 9.8.4 Using Interval Timer Mode .................................................................................. 219 Notes on Board Design...................................................................................................... 220 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Rev. 5.00, 09/03, page xxi of xliv Section 10 Bus State Controller (BSC) ......................................................................... 223 10.1 Overview ........................................................................................................................... 223 10.1.1 Features ................................................................................................................ 223 10.1.2 Block Diagram ..................................................................................................... 225 10.1.3 Pin Configuration ................................................................................................. 226 10.1.4 Register Configuration ......................................................................................... 228 10.1.5 Area Overview ..................................................................................................... 229 10.1.6 PCMCIA Support................................................................................................. 232 10.2 BSC Registers.................................................................................................................... 235 10.2.1 Bus Control Register 1 (BCR1)............................................................................ 235 10.2.2 Bus Control Register 2 (BCR2)............................................................................ 239 10.2.3 Wait State Control Register 1 (WCR1) ................................................................ 240 10.2.4 Wait State Control Register 2 (WCR2) ................................................................ 241 10.2.5 Individual Memory Control Register (MCR) ....................................................... 245 10.2.6 PCMCIA Control Register (PCR) ........................................................................ 248 10.2.7 Synchronous DRAM Mode Register (SDMR)..................................................... 252 10.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 253 10.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 255 10.2.10 Refresh Time Constant Register (RTCOR) .......................................................... 256 10.2.11 Refresh Count Register (RFCR)........................................................................... 256 10.2.12 Cautions on Accessing Refresh Control Related Registers .................................. 257 10.2.13 MCS0 Control Register (MCSCR0)..................................................................... 258 10.2.14 MCS1 Control Register (MCSCR1)..................................................................... 259 10.2.15 MCS2 Control Register (MCSCR2)..................................................................... 259 10.2.16 MCS3 Control Register (MCSCR3)..................................................................... 259 10.2.17 MCS4 Control Register (MCSCR4)..................................................................... 259 10.2.18 MCS5 Control Register (MCSCR5)..................................................................... 259 10.2.19 MCS6 Control Register (MCSCR6)..................................................................... 259 10.2.20 MCS7 Control Register (MCSCR7)..................................................................... 259 10.3 BSC Operation .................................................................................................................. 260 10.3.1 Endian/Access Size and Data Alignment ............................................................. 260 10.3.2 Description of Areas............................................................................................. 265 10.3.3 Basic Interface...................................................................................................... 268 10.3.4 Synchronous DRAM Interface ............................................................................. 276 10.3.5 Burst ROM Interface ............................................................................................ 304 10.3.6 PCMCIA Interface ............................................................................................... 307 10.3.7 Waits between Access Cycles .............................................................................. 319 10.3.8 Bus Arbitration..................................................................................................... 320 10.3.9 Bus Pull-Up .......................................................................................................... 321 10.3.10 MCS[0] to MCS[7] Pin Control ........................................................................... 323 Section 11 Direct Memory Access Controller (DMAC) .......................................... 327 11.1 Overview ........................................................................................................................... 327 Rev. 5.00, 09/03, page xxii of xliv 11.2 11.3 11.4 11.5 11.6 11.1.1 Features ................................................................................................................ 327 11.1.2 Block Diagram ..................................................................................................... 329 11.1.3 Pin Configuration ................................................................................................. 330 11.1.4 Register Configuration ......................................................................................... 331 Register Descriptions......................................................................................................... 333 11.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3)........................................... 333 11.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) .................................. 334 11.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) ......................... 335 11.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) ................................... 336 11.2.5 DMA Operation Register (DMAOR) ................................................................... 343 Operation........................................................................................................................... 345 11.3.1 DMA Transfer Flow............................................................................................. 345 11.3.2 DMA Transfer Requests....................................................................................... 347 11.3.3 Channel Priority ................................................................................................... 349 11.3.4 DMA Transfer Types ........................................................................................... 352 11.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 363 11.3.6 Source Address Reload Function ......................................................................... 372 11.3.7 DMA Transfer Ending Conditions ....................................................................... 374 Compare Match Timer (CMT) .......................................................................................... 376 11.4.1 Overview .............................................................................................................. 376 11.4.2 Register Descriptions ........................................................................................... 377 11.4.3 Operation.............................................................................................................. 380 11.4.4 Compare Match .................................................................................................... 381 Examples of Use................................................................................................................ 383 11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory ........ 383 11.5.2 Example of DMA Transfer between A/D Converter and External Memory ........ 384 11.5.3 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address On)........................................................................................... 385 Usage Notes....................................................................................................................... 387 Section 12 Timer (TMU) ................................................................................................... 389 12.1 Overview ........................................................................................................................... 389 12.1.1 Features ................................................................................................................ 389 12.1.2 Block Diagram ..................................................................................................... 390 12.1.3 Pin Configuration ................................................................................................. 391 12.1.4 Register Configuration ......................................................................................... 391 12.2 TMU Registers .................................................................................................................. 392 12.2.1 Timer Output Control Register (TOCR) .............................................................. 392 12.2.2 Timer Start Register (TSTR)................................................................................ 392 12.2.3 Timer Control Registers (TCR)............................................................................ 393 12.2.4 Timer Constant Registers (TCOR) ....................................................................... 397 12.2.5 Timer Counters (TCNT)....................................................................................... 397 12.2.6 Input Capture Register (TCPR2) .......................................................................... 399 Rev. 5.00, 09/03, page xxiii of xliv 12.3 TMU Operation ................................................................................................................. 400 12.3.1 General Operation ................................................................................................ 400 12.3.2 Input Capture Function......................................................................................... 403 12.4 Interrupts ........................................................................................................................... 404 12.4.1 Status Flag Setting Timing ................................................................................... 404 12.4.2 Status Flag Clearing Timing................................................................................. 405 12.4.3 Interrupt Sources and Priorities ............................................................................ 405 12.5 Usage Notes....................................................................................................................... 406 12.5.1 Writing to Registers.............................................................................................. 406 12.5.2 Reading Registers................................................................................................. 406 Section 13 Realtime Clock (RTC) .................................................................................. 407 13.1 Overview ........................................................................................................................... 407 13.1.1 Features ................................................................................................................ 407 13.1.2 Block Diagram ..................................................................................................... 408 13.1.3 Pin Configuration ................................................................................................. 409 13.1.4 RTC Register Configuration................................................................................. 410 13.2 RTC Registers ................................................................................................................... 411 13.2.1 64-Hz Counter (R64CNT).................................................................................... 411 13.2.2 Second Counter (RSECCNT)............................................................................... 411 13.2.3 Minute Counter (RMINCNT) .............................................................................. 412 13.2.4 Hour Counter (RHRCNT) .................................................................................... 412 13.2.5 Day of Week Counter (RWKCNT) ...................................................................... 413 13.2.6 Date Counter (RDAYCNT).................................................................................. 414 13.2.7 Month Counter (RMONCNT).............................................................................. 414 13.2.8 Year Counter (RYRCNT) .................................................................................... 415 13.2.9 Second Alarm Register (RSECAR)...................................................................... 415 13.2.10 Minute Alarm Register (RMINAR) ..................................................................... 416 13.2.11 Hour Alarm Register (RHRAR) ........................................................................... 416 13.2.12 Day of Week Alarm Register (RWKAR)............................................................. 417 13.2.13 Date Alarm Register (RDAYAR) ........................................................................ 418 13.2.14 Month Alarm Register (RMONAR)..................................................................... 418 13.2.15 RTC Control Register 1 (RCR1) .......................................................................... 419 13.2.16 RTC Control Register 2 (RCR2) .......................................................................... 420 13.3 RTC Operation .................................................................................................................. 422 13.3.1 Initial Settings of Registers after Power-On......................................................... 422 13.3.2 Setting the Time ................................................................................................... 422 13.3.3 Reading the Time ................................................................................................. 423 13.3.4 Alarm Function .................................................................................................... 424 13.3.5 Crystal Oscillator Circuit...................................................................................... 425 13.4 Usage Notes....................................................................................................................... 426 13.4.1 Register Writing during RTC Count .................................................................... 426 13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts ............................................... 426 Rev. 5.00, 09/03, page xxiv of xliv 13.4.3 Precautions when Using RTC Module Standby ................................................... 426 Section 14 Serial Communication Interface (SCI)..................................................... 427 14.1 Overview ........................................................................................................................... 427 14.1.1 Features ................................................................................................................ 427 14.1.2 Block Diagram ..................................................................................................... 428 14.1.3 Pin Configuration ................................................................................................. 431 14.1.4 Register Configuration ......................................................................................... 432 14.2 Register Descriptions......................................................................................................... 432 14.2.1 Receive Shift Register (SCRSR) .......................................................................... 432 14.2.2 Receive Data Register (SCRDR).......................................................................... 433 14.2.3 Transmit Shift Register (SCTSR)......................................................................... 433 14.2.4 Transmit Data Register (SCTDR) ........................................................................ 434 14.2.5 Serial Mode Register (SCSMR) ........................................................................... 434 14.2.6 Serial Control Register (SCSCR) ......................................................................... 437 14.2.7 Serial Status Register (SCSSR) ............................................................................ 440 14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR) ................. 444 14.2.9 Bit Rate Register (SCBRR) .................................................................................. 446 14.3 Operation........................................................................................................................... 453 14.3.1 Overview .............................................................................................................. 453 14.3.2 Operation in Asynchronous Mode........................................................................ 455 14.3.3 Multiprocessor Communication ........................................................................... 465 14.3.4 Synchronous Operation ........................................................................................ 474 14.4 SCI Interrupts .................................................................................................................... 484 14.5 Usage Notes....................................................................................................................... 485 Section 15 Smart Card Interface...................................................................................... 489 15.1 Overview ........................................................................................................................... 489 15.1.1 Features ................................................................................................................ 489 15.1.2 Block Diagram ..................................................................................................... 490 15.1.3 Pin Configuration ................................................................................................. 491 15.1.4 Smart Card Interface Registers............................................................................. 491 15.2 Register Descriptions......................................................................................................... 492 15.2.1 Smart Card Mode Register (SCSCMR)................................................................ 492 15.2.2 Serial Status Register (SCSSR) ............................................................................ 493 15.3 Operation........................................................................................................................... 494 15.3.1 Overview .............................................................................................................. 494 15.3.2 Pin Connections.................................................................................................... 495 15.3.3 Data Format.......................................................................................................... 496 15.3.4 Register Settings................................................................................................... 497 15.3.5 Clock .................................................................................................................... 498 15.3.6 Data Transmission and Reception ........................................................................ 501 15.4 Usage Notes....................................................................................................................... 507 Rev. 5.00, 09/03, page xxv of xliv 15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 507 15.4.2 Retransmission (Receive and Transmit Modes) ................................................... 509 Section 16 Serial Communication Interface with FIFO (SCIF) ............................. 511 16.1 Overview ........................................................................................................................... 511 16.1.1 Features ................................................................................................................ 511 16.1.2 Block Diagram ..................................................................................................... 512 16.1.3 Pin Configuration ................................................................................................. 515 16.1.4 Register Configuration ......................................................................................... 516 16.2 Register Descriptions......................................................................................................... 517 16.2.1 Receive Shift Register (SCRSR) .......................................................................... 517 16.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 517 16.2.3 Transmit Shift Register (SCTSR)......................................................................... 517 16.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 518 16.2.5 Serial Mode Register (SCSMR) ........................................................................... 518 16.2.6 Serial Control Register (SCSCR) ......................................................................... 520 16.2.7 Serial Status Register (SCSSR) ............................................................................ 522 16.2.8 Bit Rate Register (SCBRR) .................................................................................. 527 16.2.9 FIFO Control Register (SCFCR).......................................................................... 534 16.2.10 FIFO Data Count Register (SCFDR) ................................................................... 536 16.3 Operation........................................................................................................................... 537 16.3.1 Overview .............................................................................................................. 537 16.3.2 Serial Operation.................................................................................................... 538 16.4 SCIF Interrupts .................................................................................................................. 550 16.5 Usage Notes....................................................................................................................... 551 Section 17 IrDA.................................................................................................................... 555 17.1 Overview ........................................................................................................................... 555 17.1.1 Features ................................................................................................................ 555 17.1.2 Block Diagram ..................................................................................................... 556 17.1.3 Pin Configuration ................................................................................................. 559 17.1.4 Register Configuration ......................................................................................... 560 17.2 Register Description .......................................................................................................... 561 17.2.1 Serial Mode Register (SCSMR) ........................................................................... 561 17.3 Operation Description ....................................................................................................... 563 17.3.1 Overview .............................................................................................................. 563 17.3.2 Transmitting ......................................................................................................... 563 17.3.3 Receiving.............................................................................................................. 564 Section 18 Pin Function Controller ................................................................................ 565 18.1 Overview ........................................................................................................................... 565 18.2 Register Configuration ...................................................................................................... 569 18.3 Register Descriptions......................................................................................................... 570 Rev. 5.00, 09/03, page xxvi of xliv 18.3.1 Port A Control Register (PACR).......................................................................... 570 18.3.2 Port B Control Register (PBCR) .......................................................................... 571 18.3.3 Port C Control Register (PCCR) .......................................................................... 572 18.3.4 Port D Control Register (PDCR) .......................................................................... 573 18.3.5 Port E Control Register (PECR)........................................................................... 574 18.3.6 Port F Control Register (PFCR) ........................................................................... 575 18.3.7 Port G Control Register (PGCR) .......................................................................... 576 18.3.8 Port H Control Register (PHCR) .......................................................................... 577 18.3.9 Port J Control Register (PJCR) ............................................................................ 579 18.3.10 Port K Control Register (PKCR) .......................................................................... 580 18.3.11 Port L Control Register (PLCR)........................................................................... 581 18.3.12 SC Port Control Register (SCPCR) ...................................................................... 582 Section 19 I/O Ports ............................................................................................................ 587 19.1 Overview ........................................................................................................................... 587 19.2 Port A ................................................................................................................................ 587 19.2.1 Register Description ............................................................................................. 587 19.2.2 Port A Data Register (PADR) .............................................................................. 588 19.3 Port B ................................................................................................................................ 589 19.3.1 Register Description ............................................................................................. 589 19.3.2 Port B Data Register (PBDR)............................................................................... 590 19.4 Port C ................................................................................................................................ 591 19.4.1 Register Description ............................................................................................. 591 19.4.2 Port C Data Register (PCDR)............................................................................... 592 19.5 Port D ................................................................................................................................ 593 19.5.1 Register Description ............................................................................................. 593 19.5.2 Port D Data Register (PDDR) .............................................................................. 594 19.6 Port E................................................................................................................................. 595 19.6.1 Register Description ............................................................................................. 595 19.6.2 Port E Data Register (PEDR) ............................................................................... 596 19.7 Port F................................................................................................................................. 597 19.7.1 Register Description ............................................................................................. 597 19.7.2 Port F Data Register (PFDR)................................................................................ 598 19.8 Port G ................................................................................................................................ 599 19.8.1 Register Description ............................................................................................. 599 19.8.2 Port G Data Register (PGDR) .............................................................................. 600 19.9 Port H ................................................................................................................................ 601 19.9.1 Register Description ............................................................................................. 601 19.9.2 Port H Data Register (PHDR) .............................................................................. 602 19.10 Port J.................................................................................................................................. 603 19.10.1 Register Description ............................................................................................. 603 19.10.2 Port J Data Register (PJDR)................................................................................. 604 19.11 Port K ................................................................................................................................ 605 Rev. 5.00, 09/03, page xxvii of xliv 19.11.1 Register Description ............................................................................................. 605 19.11.2 Port K Data Register (PKDR) .............................................................................. 606 19.12 Port L................................................................................................................................. 607 19.12.1 Register Description ............................................................................................. 607 19.12.2 Port L Data Register (PLDR) ............................................................................... 608 19.13 SC Port .............................................................................................................................. 609 19.13.1 Register Description ............................................................................................. 609 19.13.2 SC Port Data Register (SCPDR) .......................................................................... 610 Section 20 A/D Converter ................................................................................................. 613 20.1 Overview ........................................................................................................................... 613 20.1.1 Features ................................................................................................................ 613 20.1.2 Block Diagram ..................................................................................................... 614 20.1.3 Input Pins.............................................................................................................. 615 20.1.4 Register Configuration ......................................................................................... 616 20.2 Register Descriptions......................................................................................................... 617 20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 617 20.2.2 A/D Control/Status Register (ADCSR) ................................................................ 618 20.2.3 A/D Control Register (ADCR)............................................................................. 621 20.3 Bus Master Interface.......................................................................................................... 622 20.4 Operation........................................................................................................................... 623 20.4.1 Single Mode (MULTI = 0)................................................................................... 623 20.4.2 Multi Mode (MULTI = 1, SCN = 0) .................................................................... 625 20.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 627 20.4.4 Input Sampling and A/D Conversion Time .......................................................... 629 20.4.5 External Trigger Input Timing ............................................................................. 630 20.5 Interrupts ........................................................................................................................... 631 20.6 Definitions of A/D Conversion Accuracy ......................................................................... 631 20.7 Usage Notes....................................................................................................................... 632 20.7.1 Setting Analog Input Voltage ............................................................................... 632 20.7.2 Processing of Analog Input Pins .......................................................................... 632 20.7.3 Access Size and Read Data .................................................................................. 633 Section 21 D/A Converter ................................................................................................. 635 21.1 Overview ........................................................................................................................... 635 21.1.1 Features ................................................................................................................ 635 21.1.2 Block Diagram ..................................................................................................... 635 21.1.3 I/O Pins................................................................................................................. 636 21.1.4 Register Configuration ......................................................................................... 636 21.2 Register Descriptions......................................................................................................... 637 21.2.1 D/A Data Registers 0 and 1 (DADR0/1) .............................................................. 637 21.2.2 D/A Control Register (DACR)............................................................................. 637 21.3 Operation........................................................................................................................... 639 Rev. 5.00, 09/03, page xxviii of xliv Section 22 User Debugging Interface (UDI) ............................................................... 641 22.1 Overview ........................................................................................................................... 641 22.2 User Debugging Interface (UDI) ....................................................................................... 641 22.2.1 Pin Descriptions ................................................................................................... 641 22.2.2 Block Diagram ..................................................................................................... 642 22.3 Register Descriptions......................................................................................................... 642 22.3.1 Bypass Register (SDBPR).................................................................................... 643 22.3.2 Instruction Register (SDIR).................................................................................. 643 22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 644 22.4 UDI Operation................................................................................................................... 651 22.4.1 TAP Controller..................................................................................................... 651 22.4.2 Reset Configuration.............................................................................................. 652 22.4.3 UDI Reset............................................................................................................. 653 22.4.4 UDI Interrupt........................................................................................................ 653 22.4.5 Bypass .................................................................................................................. 653 22.4.6 Using UDI to Recover from Sleep Mode ............................................................. 653 22.5 Boundary Scan .................................................................................................................. 654 22.5.1 Supported Instructions.......................................................................................... 654 22.5.2 Points for Attention .............................................................................................. 655 22.6 Usage Notes....................................................................................................................... 655 22.7 Advanced User Debugger (AUD) ..................................................................................... 655 Section 23 Electrical Characteristics.............................................................................. 657 23.1 Absolute Maximum Ratings.............................................................................................. 657 23.2 DC Characteristics............................................................................................................. 659 23.3 AC Characteristics............................................................................................................. 663 23.3.1 Clock Timing........................................................................................................ 664 23.3.2 Control Signal Timing.......................................................................................... 670 23.3.3 AC Bus Timing .................................................................................................... 673 23.3.4 Basic Timing ........................................................................................................ 675 23.3.5 Burst ROM Timing .............................................................................................. 678 23.3.6 Synchronous DRAM Timing ............................................................................... 681 23.3.7 PCMCIA Timing.................................................................................................. 699 23.3.8 Peripheral Module Signal Timing ........................................................................ 706 23.3.9 UDI-Related Pin Timing ...................................................................................... 709 23.3.10 AC Characteristics Measurement Conditions....................................................... 711 23.3.11 Delay Time Variation Due to Load Capacitance.................................................. 712 23.4 A/D Converter Characteristics........................................................................................... 713 23.5 D/A Converter Characteristics........................................................................................... 713 Appendix A Pin Functions ................................................................................................ 715 A.1 A.2 Pin States ........................................................................................................................... 715 Pin Specifications .............................................................................................................. 719 Rev. 5.00, 09/03, page xxix of xliv A.3 A.4 Treatment of Unused Pins ................................................................................................. 724 Pin States in Access to Each Address Space ..................................................................... 725 Appendix B Memory-Mapped Control Registers....................................................... 739 B.1 B.2 Register Address Map ....................................................................................................... 739 Register Bits ...................................................................................................................... 745 Appendix C Product Lineup ............................................................................................. 757 Appendix D Package Dimensions................................................................................... 758 Rev. 5.00, 09/03, page xxx of xliv Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 4.1 Figure 4.2 Figure 4.3 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 7.1 Figure 8.1 Figure 8.2 Block Diagram ..................................................................................................... 6 Pin Assignment (FP-208C, FP-208E) .................................................................. 7 Pin Assignment (BP-240A).................................................................................. 8 User Mode Register Configuration ...................................................................... 20 Privileged Mode Register Configuration.............................................................. 21 General Registers ................................................................................................. 22 System Registers .................................................................................................. 23 Register Set Overview, Control Registers ............................................................ 24 Longword ............................................................................................................. 25 Data Format in Memory ....................................................................................... 25 Processor State Transitions................................................................................... 54 MMU Functions ................................................................................................... 57 Virtual Address Space Mapping........................................................................... 59 MMU Register Contents ...................................................................................... 62 Overall Configuration of the TLB ........................................................................ 63 Virtual Address and TLB Structure...................................................................... 64 TLB Indexing (IX = 1) ......................................................................................... 65 TLB Indexing (IX = 0) ......................................................................................... 66 Objects of Address Comparison ........................................................................... 67 Operation of LDTLB Instruction.......................................................................... 71 Synonym Problem ................................................................................................ 73 MMU Exception Generation Flowchart ............................................................... 78 MMU Exception Signals in Instruction Fetch ...................................................... 79 MMU Exception Signals in Data Access ............................................................. 80 Specifying Address and Data for Memory-Mapped TLB Access ........................ 82 Vector Table......................................................................................................... 86 Example of Acceptance Order of General Exceptions ......................................... 89 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers......... 92 Cache Structure .................................................................................................... 104 CCR Register Configuration ................................................................................ 106 CCR2 Register Configuration .............................................................................. 107 Cache Search Scheme (Normal Mode) ................................................................ 110 Write-Back Buffer Configuration......................................................................... 112 Specifying Address and Data for Memory-Mapped Cache Access...................... 114 Block Diagram of INTC....................................................................................... 118 Example of IRL Interrupt Connection.................................................................. 122 Interrupt Operation Flowchart .............................................................................. 144 Example of Pipeline Operations when IRL Interrupt is Accepted ....................... 148 Block Diagram of User Break Controller............................................................. 150 Canceling Standby Mode with STBCR.STBY..................................................... 189 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ......................... 192 Rev. 5.00, 09/03, page xxxi of xliv Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 8.11 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Manual Reset STATUS Output............................................................................ 193 Standby to Interrupt STATUS Output.................................................................. 194 Standby to Power-On Reset STATUS Output...................................................... 195 Standby to Manual Reset STATUS Output.......................................................... 196 Sleep to Interrupt STATUS Output ...................................................................... 196 Sleep to Power-On Reset STATUS Output.......................................................... 197 Sleep to Manual Reset STATUS Output.............................................................. 198 Hardware Standby Mode (When CA Goes Low in Normal Operation)............... 200 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) ........................................................................... 201 Block Diagram of Clock Pulse Generator ............................................................ 204 Block Diagram of WDT ....................................................................................... 214 Writing to WTCNT and WTCSR......................................................................... 217 Points for Attention when Using Crystal Resonator............................................. 220 Points for Attention when Using PLL Oscillator Circuit ..................................... 221 Block Diagram of Bus State Controller................................................................ 225 Correspondence between Logical Address Space and Physical Address Space .. 229 Physical Space Allocation .................................................................................... 231 PCMCIA Space Allocation .................................................................................. 232 Writing to RFCR, RTCSR, RTCNT, and RTCOR............................................... 257 Basic Timing of Basic Interface ........................................................................... 269 Example of 32-Bit Data-Width Static RAM Connection ..................................... 270 Example of 16-Bit Data-Width Static RAM Connection ..................................... 271 Example of 8-Bit Data-Width Static RAM Connection ....................................... 272 Basic Interface Wait Timing (Software Wait Only)............................................. 273 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1)..................................................................................................... 275 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)........ 277 Example of 64-Mbit Synchronous DRAM Connection (16-Bit Bus Width)........ 278 Basic Timing for Synchronous DRAM Burst Read ............................................. 282 Synchronous DRAM Burst Read Wait Specification Timing .............................. 283 Basic Timing for Synchronous DRAM Single Read............................................ 284 Basic Timing for Synchronous DRAM Burst Write ............................................ 286 Basic Timing for Synchronous DRAM Single Write........................................... 288 Burst Read Timing (No Precharge) ...................................................................... 291 Burst Read Timing (Same Row Address) ............................................................ 292 Burst Read Timing (Different Row Addresses) ................................................... 293 Burst Write Timing (No Precharge) ..................................................................... 294 Burst Write Timing (Same Row Address) ........................................................... 295 Burst Write Timing (Different Row Addresses) .................................................. 296 Auto-Refresh Operation ....................................................................................... 298 Synchronous DRAM Auto-Refresh Timing......................................................... 299 Synchronous DRAM Self-Refresh Timing .......................................................... 301 Rev. 5.00, 09/03, page xxxii of xliv Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12 Figure 11.13 Figure 11.14 Figure 11.15 Figure 11.16 Figure 11.17 Figure 11.18 Figure 11.19 Figure 11.20 Figure 11.21 Figure 11.22 Synchronous DRAM Mode Write Timing ........................................................... 303 Burst ROM Wait Access Timing ......................................................................... 305 Burst ROM Basic Access Timing ........................................................................ 306 Example of PCMCIA Interface ............................................................................ 308 Basic Timing for PCMCIA Memory Card Interface ............................................ 310 Wait Timing for PCMCIA Memory Card Interface ............................................. 311 Basic Timing for PCMCIA Memory Card Interface Burst Access ...................... 312 Wait Timing for PCMCIA Memory Card Interface Burst Access ....................... 313 PCMCIA Space Allocation .................................................................................. 314 Basic Timing for PCMCIA I/O Card Interface .................................................... 316 Wait Timing for PCMCIA I/O Card Interface ..................................................... 317 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................ 318 Waits between Access Cycles .............................................................................. 320 Pull-Up Timing for Pins A25 to A0 ..................................................................... 321 Pull-Up Timing for Pins D31 to D0 (Read Cycle) ............................................... 322 Pull-Up Timing for Pins D31 to D0 (Write Cycle) .............................................. 322 Block Diagram of DMAC .................................................................................... 329 DMAC Transfer Flowchart .................................................................................. 346 Round-Robin Mode.............................................................................................. 350 Changes in Channel Priority in Round-Robin Mode............................................ 351 Operation of Direct Address Mode in Dual Address Mode ................................. 353 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory). 354 Indirect Address Operation in Dual Address Mode (When External Memory Space has a 16-Bit Width).................................................................................... 355 Example of Transfer Timing in the Indirect Address Mode in Dual Address Mode .................................................................................................................... 356 Data Flow in Single Address Mode...................................................................... 357 Example of DMA Transfer Timing in Single Address Mode .............................. 358 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer, External Memory Space (Ordinary Memory) External Device with DACK) . 359 Example of DMA Transfer in Cycle-Steal Mode................................................. 360 Example of Transfer in Burst Mode ..................................................................... 360 Bus State when Multiple Channels Are Operating............................................... 362 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ..................................... 365 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ..................................... 366 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles)............................................................................................................... 367 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) . 368 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ...................................... 369 Burst Mode, Level Input ...................................................................................... 370 Burst Mode, Edge Input ....................................................................................... 371 Source Address Reload Function Diagram........................................................... 372 Rev. 5.00, 09/03, page xxxiii of xliv Figure 11.23 Figure 11.24 Figure 11.25 Figure 11.26 Figure 11.27 Figure 11.28 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Timing Chart of Source Address Reload Function............................................... 373 Block Diagram of CMT ....................................................................................... 376 Counter Operation ................................................................................................ 380 Count Timing ....................................................................................................... 381 CMF Setting Timing ............................................................................................ 382 Timing of CMF Clearing by the CPU .................................................................. 382 Block Diagram of TMU ....................................................................................... 390 Setting the Count Operation ................................................................................. 401 Auto-Reload Count Operation.............................................................................. 402 Count Timing when Operating on Internal Clock ................................................ 402 Count Timing when Operating on External Clock (Both Edges Detected) .......... 403 Count Timing when Operating on On-Chip RTC Clock ...................................... 403 Operation Timing when Using Input Capture Function (Using TCLK Rising Edge) .................................................................................................................... 404 UNF Setting Timing............................................................................................. 404 Status Flag Clearing Timing................................................................................. 405 Block Diagram of RTC ........................................................................................ 408 Setting the Time ................................................................................................... 422 Reading the Time ................................................................................................. 423 Using the Alarm Function .................................................................................... 424 Example of Crystal Oscillator Circuit Connection............................................... 425 Using Periodic Interrupt Function ........................................................................ 426 Block Diagram of SCI .......................................................................................... 428 SCPT[1]/SCK0 Pin .............................................................................................. 429 SCPT[0]/TxD0 Pin............................................................................................... 430 SCPT[0]/RxD0 Pin............................................................................................... 431 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ............................................................................ 455 Output Clock and Serial Data Timing (Asynchronous Mode) ............................. 457 Sample Flowchart for SCI Initialization............................................................... 458 Sample Flowchart for Transmitting Serial Data ................................................... 459 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) .............................................................................. 461 Sample Flowchart for Receiving Serial Data ....................................................... 462 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) .. 465 Communication Among Processors Using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) .................................................. 466 Sample Flowchart for Transmitting Multiprocessor Serial Data .......................... 467 Example of SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) .................................................................. 468 Sample Flowchart for Receiving Multiprocessor Serial Data .............................. 470 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)........................................................................................................ 472 Rev. 5.00, 09/03, page xxxiv of xliv Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Figure 15.10 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 Figure 16.10 Figure 16.11 Figure 16.12 Figure 16.13 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 Figure 19.7 Data Format in Synchronous Communication ..................................................... 474 Sample Flowchart for SCI Initialization............................................................... 476 Sample Flowchart for Transmitting Serial Data ................................................... 477 Example of SCI Transmit Operation .................................................................... 478 Sample Flowchart for Receiving Serial Data ....................................................... 480 Example of SCI Receive Operation...................................................................... 482 Sample Flowchart for Transmitting/Receiving Serial Data.................................. 483 Receive Data Sampling Timing in Asynchronous Mode ..................................... 486 Block Diagram of Smart Card Interface............................................................... 490 Pin Connection Diagram for Smart Card Interface .............................................. 495 Data Format for Smart Card Interface.................................................................. 496 Waveform of Start Character................................................................................ 498 Initialization Flowchart (Example)....................................................................... 502 Transmission Flowchart ....................................................................................... 504 Reception Flowchart (Example)........................................................................... 506 Receive Data Sampling Timing in Smart Card Mode .......................................... 508 Retransmission in SCI Receive Mode .................................................................. 509 Retransmission in SCI Transmit Mode ................................................................ 510 Block Diagram of SCIF........................................................................................ 512 SCPT[5]/SCK2 Pin .............................................................................................. 513 SCPT[4]/TxD2 Pin............................................................................................... 514 SCPT[4]/RxD2 Pin............................................................................................... 515 Sample Flowchart for SCIF Initialization ............................................................ 540 Sample Flowchart for Transmitting Serial Data ................................................... 542 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)..................... 544 Example of Operation Using Modem Control (CTS)........................................... 544 Sample Flowchart for Receiving Serial Data ....................................................... 546 Sample Flowchart for Receiving Serial Data (cont)............................................. 547 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)............. 549 Example of Operation Using Modem Control (RTS)........................................... 549 Receive Data Sampling Timing in Asynchronous Mode ..................................... 552 Block Diagram of IrDA........................................................................................ 556 SCPT[3]/SCK1 Pin .............................................................................................. 557 SCPT[2]/TxD1 Pin............................................................................................... 558 SCPT[2]/RxD1 Pin............................................................................................... 559 Transmit/Receive Operation................................................................................. 564 Port A ................................................................................................................... 587 Port B ................................................................................................................... 589 Port C ................................................................................................................... 591 Port D ................................................................................................................... 593 Port E.................................................................................................................... 595 Port F.................................................................................................................... 597 Port G ................................................................................................................... 599 Rev. 5.00, 09/03, page xxxv of xliv Figure 19.8 Figure 19.9 Figure 19.10 Figure 19.11 Figure 19.12 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Figure 20.9 Figure 20.10 Figure 21.1 Figure 21.2 Figure 22.1 Figure 22.2 Figure 22.3 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Figure 23.8 Figure 23.9 Figure 23.10 Figure 23.11 Figure 23.12 Figure 23.13 Figure 23.14 Figure 23.15 Figure 23.16 Figure 23.17 Figure 23.18 Port H ................................................................................................................... 601 Port J .................................................................................................................... 603 Port K ................................................................................................................... 605 Port L.................................................................................................................... 607 SC Port ................................................................................................................. 609 Block Diagram of A/D Converter ........................................................................ 614 A/D Data Register Access Operation (Reading H'AA40) .................................... 622 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ......... 624 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) ............................................................................................................... 626 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ............................................................................................................... 628 A/D Conversion Timing ....................................................................................... 629 External Trigger Input Timing ............................................................................. 630 Definitions of A/D Conversion Accuracy ............................................................ 632 Example of Analog Input Protection Circuit ........................................................ 633 Analog Input Pin Equivalent Circuit .................................................................... 633 Block Diagram of D/A Converter ........................................................................ 635 Example of D/A Converter Operation.................................................................. 639 Block Diagram of UDI ......................................................................................... 642 TAP Controller State Transitions ......................................................................... 651 UDI Reset............................................................................................................. 653 EXTAL Clock Input Timing ................................................................................ 665 CKIO Clock Input Timing ................................................................................... 665 CKIO Clock Output Timing................................................................................. 665 Power-on Oscillation Settling Time ..................................................................... 666 Oscillation Settling Time at Standby Return (Return by Reset)........................... 666 Oscillation Settling Time at Standby Return (Return by NMI)............................ 667 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0, PINT0/1, IRL3 to IRL0)....................................................................................... 667 PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) .. 668 PLL Synchronization Settling Time during Standby Recovery (IRQ/IRL or PINT0/PINT1 Interrupt)....................................................................................... 668 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified ............................................................................................................... 669 Reset Input Timing............................................................................................... 671 Interrupt Signal Input Timing............................................................................... 671 IRQOUT Timing .................................................................................................. 671 Bus Release Timing.............................................................................................. 672 Pin Drive Timing at Standby................................................................................ 672 Basic Bus Cycle (No Wait) .................................................................................. 675 Basic Bus Cycle (One Wait)................................................................................. 676 Basic Bus Cycle (External Wait, WAITSEL = 1) ................................................ 677 Rev. 5.00, 09/03, page xxxvi of xliv Figure 23.19 Figure 23.20 Figure 23.21 Figure 23.22 Figure 23.23 Figure 23.24 Figure 23.25 Figure 23.26 Figure 23.27 Figure 23.28 Figure 23.29 Figure 23.30 Figure 23.31 Figure 23.32 Figure 23.33 Figure 23.34 Figure 23.35 Figure 23.36 Figure 23.37 Figure 23.38 Figure 23.39 Figure 23.40 Figure 23.41 Figure 23.42 Figure 23.43 Figure 23.44 Figure 23.45 Figure 23.46 Burst ROM Bus Cycle (No Wait) ........................................................................ 678 Burst ROM Bus Cycle (Two Waits) .................................................................... 679 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 680 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) .. 681 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) .. 682 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1) ................................................................. 683 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0) ................................................................. 684 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)............ 685 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)............ 686 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) ........................................................................... 687 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) ........................................................................... 688 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1).................................................................................. 689 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2).................................................................................. 690 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1) .................................................. 691 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) .................................................. 692 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) ............................................................................................................... 693 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0) ............................................................................... 694 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1) ............................................................................... 695 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 696 Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1) ......................... 697 Synchronous DRAM Mode Register Write Cycle ............................................... 698 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 699 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1)..................................................................................................... 700 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 701 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1)........................................................................... 702 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)...................................... 703 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1)..................................................................................................... 704 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1)..................................................................................................... 705 Rev. 5.00, 09/03, page xxxvii of xliv Figure 23.47 Figure 23.48 Figure 23.49 Figure 23.50 Figure 23.51 Figure 23.52 Figure 23.53 Figure 23.54 Figure 23.55 Figure 23.56 Figure 23.57 Figure 23.58 Figure 23.59 Figure 23.60 Figure D.1 Figure D.2 Figure D.3 TCLK Input Timing ............................................................................................. 707 TCLK Clock Input Timing................................................................................... 707 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................ 707 SCK Input Clock Timing ..................................................................................... 707 SCI I/O Timing in Clock Synchronous Mode ...................................................... 708 I/O Port Timing .................................................................................................... 708 DREQ Input Timing............................................................................................. 708 DRAK Output Timing.......................................................................................... 709 TCK Input Timing................................................................................................ 709 TRST Input Timing (Reset Hold)......................................................................... 710 UDI Data Transfer Timing ................................................................................... 710 ASEMD0 Input Timing........................................................................................ 710 Output Load Circuit.............................................................................................. 711 Load Capacitance vs. Delay Time........................................................................ 712 Package Dimensions (FP-208C)........................................................................... 758 Package Dimensions (FP-208E)........................................................................... 759 Package Dimensions (BP-240A).......................................................................... 760 Rev. 5.00, 09/03, page xxxviii of xliv Tables Table 1.1 Table 1.2 Table 1.3 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 3.1 Table 3.2 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 7.1 Table 7.2 Table 8.1 SH7709S Features .................................................................................................. 2 Characteristics......................................................................................................... 5 SH7709S Pin Function ........................................................................................... 9 Initial Register Values ............................................................................................ 22 Addressing Modes and Effective Addresses........................................................... 28 Instruction Formats ................................................................................................. 32 Classification of Instructions .................................................................................. 35 Instruction Code Format ......................................................................................... 38 Data Transfer Instructions ...................................................................................... 39 Arithmetic Instructions ........................................................................................... 41 Logic Operation Instructions .................................................................................. 44 Shift Instructions..................................................................................................... 45 Branch Instructions ................................................................................................. 46 System Control Instructions.................................................................................... 47 Instruction Code Map ............................................................................................. 50 Register Configuration............................................................................................ 61 Access States Designated by D, C, and PR Bits ..................................................... 68 Register Configuration............................................................................................ 85 Exception Event Vectors ........................................................................................ 87 Exception Codes ..................................................................................................... 90 Types of Reset ........................................................................................................ 95 Cache Specifications............................................................................................... 103 LRU and Way Replacement (When the cache lock function is not used) .............. 105 Register Configuration............................................................................................ 105 Way Replacement when PREF Instruction Ended Up in a Cache Miss ................. 107 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss....................................................................................................... 108 LRU and Way Replacement (when W2LOCK=1) ................................................. 108 LRU and Way Replacement (when W3LOCK=1) ................................................. 108 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)..................... 108 INTC Pins ............................................................................................................... 119 INTC Registers ....................................................................................................... 120 IRL3-IRL0/IRLS3-IRLS0 Pins and Interrupt Levels ............................................ 123 Interrupt Exception Handling Sources and Priority (IRQ Mode) ........................... 126 Interrupt Exception Handling Sources and Priority (IRL Mode)............................ 128 Interrupt Levels and INTEVT Codes...................................................................... 130 Interrupt Request Sources and IPRA-IPRE............................................................ 131 Interrupt Response Time......................................................................................... 146 Register Configuration............................................................................................ 151 Data Access Cycle Addresses and Operand Size Comparison Conditions............. 171 Power-Down Modes ............................................................................................... 182 Rev. 5.00, 09/03, page xxxix of xliv Table 8.2 Table 8.3 Table 8.4 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Pin Configuration.................................................................................................... 183 Register Configuration............................................................................................ 183 Register States in Standby Mode ............................................................................ 188 CPG Pins and Functions ......................................................................................... 206 CPG Register .......................................................................................................... 206 Clock Operating Modes .......................................................................................... 207 Available Combinations of Clock Mode and FRQCR Values................................ 208 Register Configuration............................................................................................ 214 BSC Pins................................................................................................................. 226 BSC Registers......................................................................................................... 228 Physical Address Space Map.................................................................................. 230 Correspondence between External Pins (MD4 and MD3) and Memory Size......... 231 PCMCIA Interface Characteristics ......................................................................... 232 PCMCIA Support Interface .................................................................................... 233 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 260 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 261 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 262 32-Bit External Device/Little-Endian Access and Data Alignment........................ 263 16-Bit External Device/Little-Endian Access and Data Alignment........................ 263 8-Bit External Device/Little-Endian Access and Data Alignment.......................... 264 Relationship between Bus Width, AMX Bits, and Address Multiplex Output ....... 279 Example of Correspondence between SH7709S and Synchronous DRAM Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width)).......................................... 281 Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0-7).............................. 324 Table 11.1 DMAC Pins ............................................................................................................ 330 Table 11.2 DMAC Registers .................................................................................................... 331 Table 11.3 Selecting External Request Modes with RS Bits .................................................... 347 Table 11.4 Selecting On-Chip Peripheral Module Request Modes with RS3-0 Bits................ 348 Table 11.5 Supported DMA Transfers...................................................................................... 352 Table 11.6 Relationship between Request Modes and Bus Modes by DMA Transfer Category ................................................................................................................. 361 Table 11.7 Register Configuration............................................................................................ 377 Table 11.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory ............................................................................................. 383 Table 11.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory ............................................................................ 384 Table 11.10 Values in DMAC after End of Fourth Transfer ...................................................... 385 Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter............................................................................... 386 Table 12.1 TMU Pin................................................................................................................. 391 Table 12.2 TMU Registers........................................................................................................ 391 Table 12.3 TMU Interrupt Sources........................................................................................... 405 Table 13.1 RTC Pins................................................................................................................. 409 Rev. 5.00, 09/03, page xl of xliv Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 16.7 Table 16.8 Table 16.9 Table 16.10 Table 17.1 Table 17.2 Table 18.1 Table 18.2 RTC Registers......................................................................................................... 410 Day-of-Week Codes (RWKCNT) .......................................................................... 413 Day-of-Week Codes (RWKAR) ............................................................................. 417 Recommended Oscillator Circuit Constants (Recommended Values).................... 425 SCI Pins ................................................................................................................. 431 SCI Registers .......................................................................................................... 432 SCSMR Settings ..................................................................................................... 446 Bit Rates and SCBRR Settings in Asynchronous Mode ......................................... 447 Bit Rates and SCBRR Settings in Synchronous Mode ........................................... 450 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) ............................................................................................ 451 Maximum Bit Rates with External Clock Input (Asynchronous Mode)................. 452 Maximum Bit Rates with External Clock Input (Synchronous Mode) ................... 452 Serial Mode Register Settings and SCI Communication Formats .......................... 454 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................. 454 Serial Communication Formats (Asynchronous Mode) ......................................... 456 Receive Error Conditions and SCI Operation......................................................... 464 SCI Interrupt Sources ............................................................................................. 484 SCSSR Status Flags and Transfer of Receive Data ................................................ 485 Smart Card Interface Pins ....................................................................................... 491 Registers ................................................................................................................. 491 Register Settings for Smart Card Interface ............................................................. 497 Relationship of n to CKS1 and CKS0..................................................................... 499 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0)................................. 499 Examples of SCBRR Settings for Bit Rate B (Bits/s) (n = 0)................................. 499 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ....................... 500 Register Set Values and SCK Pin ........................................................................... 500 Smart Card Mode Operating State and Interrupt Sources....................................... 507 SCIF Pins................................................................................................................ 515 SCIF Registers ........................................................................................................ 516 SCSMR Settings ..................................................................................................... 528 Bit Rates and SCBRR Settings ............................................................................... 528 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) ............................................................................................ 532 Maximum Bit Rates with External Clock Input (Asynchronous Mode)................. 533 SCSMR Settings and SCIF Communication Formats ............................................ 537 SCSCR Settings and SCIF Clock Source Selection................................................ 538 Serial Communication Formats .............................................................................. 538 SCIF Interrupt Sources ........................................................................................... 550 IrDA Pins................................................................................................................ 559 IrDA Registers ........................................................................................................ 560 List of Multiplexed Pins ......................................................................................... 565 Pin Function Controller Registers........................................................................... 569 Rev. 5.00, 09/03, page xli of xliv Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 Table 19.10 Table 19.11 Table 19.12 Table 19.13 Table 19.14 Table 19.15 Table 19.16 Table 19.17 Table 19.18 Table 19.19 Table 19.20 Table 19.21 Table 19.22 Table 19.23 Table 19.24 Table 20.1 Table 20.2 Table 20.3 Table 20.4 Table 20.5 Table 20.6 Table 21.1 Table 21.2 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 23.1 Table 23.2 Table 23.3 Table 23.4 Table 23.5 Table 23.6 Table 23.7 Port A Register ....................................................................................................... 587 Port A Data Register (PADR) Read/Write Operations ........................................... 588 Port B Register........................................................................................................ 589 Port B Data Register (PBDR) Read/Write Operations ........................................... 590 Port C Register........................................................................................................ 591 Port C Data Register (PCDR) Read/Write Operations ........................................... 592 Port D Register ....................................................................................................... 593 Port D Data Register (PDDR) Read/Write Operations ........................................... 594 Port E Register........................................................................................................ 595 Port E Data Register (PEDR) Read/Write Operations ............................................ 596 Port F Register ........................................................................................................ 597 Port F Data Register (PFDR) Read/Write Operations ............................................ 598 Port G Register ....................................................................................................... 599 Port G Data Register (PGDR) Read/Write Operations ........................................... 600 Port H Register ....................................................................................................... 601 Port H Data Register (PHDR) Read/Write Operations ........................................... 602 Port J Register......................................................................................................... 603 Port J Data Register (PJDR) Read/Write Operations.............................................. 604 Port K Register ....................................................................................................... 605 Port K Data Register (PKDR) Read/Write Operations ........................................... 606 Port L Register ........................................................................................................ 607 Port L Data Register (PLDR) Read/Write Operation ............................................. 608 SC Port Register ..................................................................................................... 609 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 611 A/D Converter Pins................................................................................................. 615 A/D Converter Registers......................................................................................... 616 Analog Input Channels and A/D Data Registers .................................................... 617 A/D Conversion Time (Single Mode)..................................................................... 630 Analog Input Pin Ratings........................................................................................ 634 Relationship between Access Size and Read Data ................................................. 634 D/A Converter Pins................................................................................................. 636 D/A Converter Registers......................................................................................... 636 UDI Registers ......................................................................................................... 643 UDI Commands ...................................................................................................... 644 Pins of this LSI and Boundary Scan Register Bits.................................................. 645 Reset Configuration ................................................................................................ 652 Absolute Maximum Ratings ................................................................................... 657 DC Characteristics .................................................................................................. 659 Permitted Output Current Values............................................................................ 662 Operating Frequency Range ................................................................................... 663 Clock Timing .......................................................................................................... 664 Control Signal Timing ............................................................................................ 670 Bus Timing ............................................................................................................. 673 Rev. 5.00, 09/03, page xlii of xliv Table 23.8 Table 23.9 Table 23.10 Table 23.11 Table A.1 Table A.2 Table A.3 Table A.4 Table A.5 Table A.6 Table A.7 Table A.8 Table A.9 Table A.10 Table B.1 Table B.2 Table C.1 Peripheral Module Signal Timing........................................................................... 706 UDI-Related Pin Timing......................................................................................... 709 A/D Converter Characteristics................................................................................ 713 D/A Converter Characteristics................................................................................ 713 Pin States during Resets, Power-Down States, and Bus-Released State................. 715 Pin Specifications ................................................................................................... 719 Pin States (Ordinary Memory/Little Endian).......................................................... 725 Pin States (Ordinary Memory/Big Endian)............................................................. 727 Pin States (Burst ROM/Little Endian) .................................................................... 729 Pin States (Burst ROM/Big Endian) ....................................................................... 731 Pin States (Synchronous DRAM/Little Endian) ..................................................... 733 Pin States (Synchronous DRAM/Big Endian) ........................................................ 734 Pin States (PCMCIA/Little Endian)........................................................................ 735 Pin States (PCMCIA/Big Endian) .......................................................................... 737 Memory-Mapped Control Registers ....................................................................... 739 Register Bits ........................................................................................................... 745 SH7709S Models.................................................................................................... 757 Rev. 5.00, 09/03, page xliii of xliv Rev. 5.00, 09/03, page xliv of xliv Section 1 Overview and Pin Functions 1.1 SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperHTM architecture CPU as its core that has an on-chip multiplier, cache memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration such as a timer, a realtime clock, an interrupt controller, and a serial communication interface. This LSI includes data protection, virtual memory, and other functions provided by incorporating an MMU into a SuperH Series microprocessor (SH-1 or SH-2). High-speed data transfers can be performed by an on-chip direct memory access controller (DMAC) and an external memory access support function enables direct connection to different types of memory. The SH7709S microprocessor also supports an infrared communication function, an A/D converter, and a D/A converter. A powerful built-in power management function keeps power consumption low, even during highspeed operation. This LSI can run at six times the frequency of the system bus operating speed, making it optimum for electrical devices such as PDAs that require both high speed and low power. The features of this LSI is listed in table 1.1. The specifications are shown in table 1.2. Note: SuperH is a trademark of Renesas Technology, Corp. Rev. 5.00, 09/03, page 1 of 760 Table 1.1 Item CPU SH7709S Features Features * * * * Original Renesas Technology SuperH architecture Object code level with SH-1, SH-2, and SH-3 Series 32-bit internal data bus General-register files Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers Four 32-bit system registers * RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture Delayed branch instructions Instruction set based on C language * * * * Instruction execution time: one instruction/cycle for basic instructions Logical address space: 4 Gbytes Space identifier ASID: 8 bits, 256 logical address space Five-stage pipeline Clock mode: An input clock can be selected from the external input (EXTAL or CKIO) or crystal oscillator. Three types of clocks generated: CPU clock: 1-24 times the input clock, maximum 200 MHz Bus clock: 1-4 times the input clock, maximum 66.67 MHz Peripheral clock: 1/4-4 times the input clock, maximum 33.34 MHz * Power-down modes: Sleep mode Standby mode Module standby mode * One-channel watchdog timer 4 Gbytes of address space, 256 address spaces (ASID 8 bits) Page unit sharing Supports multiple page sizes: 1, 4 kbytes 128-entry, 4-way set associative TLB Supports software selection of replacement method and random-replacement algorithms Clock pulse generator (CPG) * * Memory management unit (MMU) * * * * * Rev. 5.00, 09/03, page 2 of 760 Item Cache memory Features * * * * * 16-kbyte cache, mixed instruction/data 256 entries, 4-way set associative, 16-byte block length Write-back, write-through, LRU replacement algorithm 1-stage write-back buffer Maximum 2 ways of the cache can be locked 23 external interrupt pins (NMI, IRQ5-IRQ0, PINT15 to PINT0) On-chip peripheral interrupts: set priority levels for each module 2 break channels Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Physical address space divided into six areas (area 0, areas 2 to 6), each a maximum of 64 Mbytes, with the following features settable for each area: Bus size (8, 16, or 32 bits) Number of wait cycles (also supports a hardware wait function) Setting the type of space enables direct connection to SRAM, Synchronous DRAM, and burst ROM Supports PCMCIA interface (2 channels) Outputs chip select signal (CS0, CS2-CS6) for corresponding area * Synchronous DRAM refresh function Programmable refresh interval Support self-refresh mode * * Synchronous DRAM burst access function Usable as either big or little endian machine E10A emulator support JTAG-compliant Realtime branch address trace 1-kB on-chip RAM for fast emulation program execution 3-channel auto-reload-type 32-bit timer Input capture function 6 types of counter input clocks can be selected Maximum resolution: 2 MHz Built-in clock, calendar functions, and alarm functions On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt cycle) of 1/256 second Interrupt controller (INTC) User break controller (UBC) * * * * * Bus state controller (BSC) * User-debugging Interface (UDI) * * * * Timer (TMU) * * * * Realtime clock (RTC) * * Rev. 5.00, 09/03, page 3 of 760 Item Features Asynchronous mode or clock synchronous mode can be selected Full-duplex communication Supports smart card interface 16-byte FIFO for transmission/reception DMA can be transferred IrDA: interface based on 1.0 16-byte FIFO for transmission/reception DMA can be transferred Hardware flow control 4 channels Burst mode and cycle-steal mode Data transfer size: 8-/16-/32-bit and 16-byte Twelve 8-bit ports 10 bits 4 LSB, 8 channels Conversion time: 16 s Input range: 0-AVcc (max. 3.6 V) 8 bits 4 LSB, 2 channels Conversion time: 10 s Output range: 0-AVcc (max. 3.6 V) Power Supply Voltage Abbr. I/O Internal Operating Frequency Model Name Serial communi- * cation interface 0 * (SCI0/SCI) * Serial communi- * cation interface 1 * (SCI1/IrDA) * Serial communi- * cation interface 2 * (SCI2/SCIF) * Direct memory * access controller * (DMAC) * I/O port A/D converter (ADC) * * * * D/A converter (DAC) * * * Product lineup Package SH7709S 3.30.3 V 2.00.15 V* 200 MHz 1.90.15 V 167 MHz HD6417709SHF200B 208-pin plastic HQFP (FP-208E) HD6417709SF167B 208-pin plastic LQFP (FP-208C) HD6417709SBP167B 240-pin CSP (BP-240A) 1.8+0.25 V 1.8-0.15 V 133 MHz HD6417709SF133B 208-pin plastic LQFP (FP-208C) HD6417709SBP133B 240-pin CSP (BP-240A) 1.7+0.25 V 1.7-0.15 V 100 MHz HD6417709SF100B 208-pin plastic LQFP (FP-208C) HD6417709SBP100B 240-pin CSP (BP-240A) Note: * 2.0 (+0.15, -0.1) V when an IRL or IRLS interrupt is used. Rev. 5.00, 09/03, page 4 of 760 Table 1.2 Item Characteristics Characteristics * I/O: 3.3 0.3 V Internal: 2.0 0.15 V (200 MHz model)*, 1.90.15 V (167 MHz model), 1.8 (+0.25, -0.15) V (133 MHz model), 1.7(+0.25, -0.15) V (100 MHz model) Internal frequency: maximum 200 MHz(200 MHz model), 167 MHz (167 MHz model) 133.34 MHz (133 MHz model), 100 MHz (100 MHz model); external frequency: maximum 66.67 MHz 0.25-m CMOS/5-layer metal Power supply voltage Operating frequency * Process * Note: * 2.0 (+0.15, -0.1) V when an IRL or IRLS interrupt is used. Rev. 5.00, 09/03, page 5 of 760 1.2 Block Diagram MMU SH-3 CPU I bus 1 TLB L bus UBC CCN AUD CACHE Peripheral bus 1 SCI TMU BRIDGE RTC UDI BSC IrDA INTC I bus 2 SCIF DMAC CPG/WDT Peripheral bus 2 ADC CMT DAC External bus interface I/O port Legend: ADC: AUD: BSC: CACHE: CCN: CMT: CPG/WDT: CPU: DAC: DMAC: UDI: A/D converter Advanced user debugger Bus state controller Cache memory Cache memory controller Compare match timer Clock pulse generator/watchdog timer Central processing unit D/A converter Direct memory access controller User debugging interface INTC: IrDA: MMU: RTC: SCI: SCIF: TLB: TMU: UBC: Interrupt controller Serial communicatiion interface (with IrDA) Memory management unit Realtime clock Serial communication interface (with smart card interface) Serial communication interface (with FIFO) Address translation buffer Timer unit User break controller Figure 1.1 Block Diagram Rev. 5.00, 09/03, page 6 of 760 1.3 1.3.1 Pin Description Pin Assignment EXTAL XTAL VCC VSS VSS AUDCK/PTH[6] VCC-PLL2 CAP2 VSS-PLL2 VSS-PLL1 CAP1 VCC-PLL1 MD0 IRLS0/PTF[0]/PINT[8] IRLS1/PTF[1]/PINT[9] IRLS2/PTF[2]/PINT[10] IRLS3/PTF[3]/PINT[11] TCK/PTF[4]/PINT[12] TDI/PTF[5]/PINT[13] TMS/PTF[6]/PINT[14] TRST/PTF[7]/PINT[15] AUDATA[0]/PTG[0] VCC AUDATA[1]/PTG[1] VSS AUDATA[2]/PTG[2] AUDATA[3]/PTG[3] PTG[4]/CKIO2 ASEBRKAK/PTG[5] ASEMD0/PTG[6] IOIS16/PTG[7] ADTRG/PTH[5] RESETM WAIT BREQ BACK TDO/PTE[0] PTE[1] RAS3U/PTE[2] PTE[3] PTE[6] DACK1/PTD[7] DACK0/PTD[5] PTJ[5] PTJ[4] VCCQ CASU/PTJ[3] VSSQ CASL/PTJ[2] PTJ[1] RAS3L/PTJ[0] CKE/PTK[5] 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VSSQ CKIO VCCQ TxD0/SCPT[0] SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3] TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] VSS RXD2/SCPT[4] VCC CTS2/IRQ5/SCPT[7] MCS[7]/PTC[7]/PINT[7] MCS[6]/PTC[6]/PINT[6] MCS[5]/PTC[5]/PINT[5] MCS[4]/PTC[4]/PINT[4] VSSQ WAKEUP/PTD[3] VCCQ RESETOUT/PTD[2] MCS[3]/PTC[3]/PINT[3] MCS[2]/PTC[2]/PINT[2] MCS[1]/PTC[1]/PINT[1] MCS[0]/PTC[0]/PINT[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP CA MD3 MD4 MD5 AVSS AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVCC AN[6]/DA[1]/PTL[6] AN[7]/DA[0]/PTL[7] AVSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 SH7709S FP-208C FP-208E (Top view) INDEX MARK 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CE2B/PTE[5] CE2A/PTE[4] CS6/CE1B CS5/CE1A/PTK[3] CS4/PTK[2] CS3/PTK[1] CS2/PTK[0] VCCQ CS0/MCS0 VSSQ AUDSYNC/PTE[7] RD/WR WE3/DQMUU/ICIOWR/PTK[7] WE2/DQMUL/ICIORD/PTK[6] WE1/DOMLU/WE WE0/DQMLL RD BS/PTK[4] A25 VCCQ A24 VSSQ A23 VCC A22 VSS A21 A20 A19 A18 A17 A16 A15 VCCQ A14 VSSQ A13 A12 A11 A10 A9 A8 A7 A6 A5 VCCQ A4 VSSQ A3 A2 A1 A0 MD1 MD2 VCC-RTC XTAL2 EXTAL2 VSS-RTC NMI IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VSSQ D25/PTB[1] VCCQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] VSS D19/PTA[3] VCC D18/PTA[2] D17/PTA[1] D16/PTA[0] VSSQ D15 VCCQ D14 D13 D12 D11 D10 D9 D8 D7 D6 VSSQ D5 VCCQ D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Figure 1.2 Pin Assignment (FP-208C, FP-208E) Rev. 5.00, 09/03, page 7 of 760 A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B CD E F GH J K L MN P R T U VW 19 18 17 16 15 14 13 12 SH7709S BP-240A (Top view) 11 10 9 8 7 6 5 4 3 2 1 B CD E F GH J K L MN P R T U VW Note: The pin area enclosed in broken lines is an inner view. Figure 1.3 Pin Assignment (BP-240A) Rev. 5.00, 09/03, page 8 of 760 1.3.2 Table 1.3 Pin Function SH7709S Pin Function Number of Pins FP-208C FP-208E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 BP-240A D2 C2 E2 D1 D3 E1 C3 E3 E4 F1 F2 F3 F4 G1 G2 G3 G4 H1 H2 H3 H4 J1 J2 J4 J3 K2 Pin Name MD1 MD2 1 Vcc-RTC* I/O I I -- O I Description Clock mode setting Clock mode setting RTC power supply (* ) On-chip RTC crystal oscillator pin On-chip RTC crystal oscillator 6 pin* RTC power supply (0 V) Nonmaskable interrupt request External interrupt request/input port H External interrupt request/input port H External interrupt request/input port H External interrupt request/input port H External interrupt request/input port H Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Input/output power supply (0 V) Data bus / input/output port B Input/output power supply (3.3 V) Data bus / input/output port B Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Rev. 5.00, 09/03, page 9 of 760 3 XTAL2 EXTAL2 Vss-RTC* NMI IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VssQ D25/PTB[1] VccQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] 1 -- I I I I I I I/O I/O I/O I/O I/O I/O -- I/O -- I/O I/O I/O I/O I/O Number of Pins FP-208C FP-208E 27 -- 28 29 -- 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BP-240A K3 K4 K1 L3 L4 L2 L1 M4 M3 M2 M1 N4 N3 N2 N1 P4 P3 P2 P1 R4 R3 T4 R1 T3 T1 R2 U2 T2 V4 V3 V5 W4 Pin Name Vss Vss D19/PTA[3] Vcc Vcc D18/PTA[2] D17/PTA[1] D16/PTA[0] VssQ D15 VccQ D14 D13 D12 D11 D10 D9 D8 D7 D6 VssQ D5 VccQ D4 D3 D2 D1 D0 A0 A1 A2 A3 I/O -- -- I/O -- -- I/O I/O I/O -- I/O -- I/O I/O I/O I/O I/O I/O I/O I/O I/O -- I/O -- I/O I/O I/O I/O I/O O O O O Description Power supply (0 V) Power supply (0 V) Data bus / input/output port A Power supply (1.9 V/1.8 V* ) 3 Power supply (* ) Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Address bus Address bus Address bus Address bus 3 Rev. 5.00, 09/03, page 10 of 760 Number of Pins FP-208C FP-208E 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 -- 80 81 -- 82 83 84 85 86 BP-240A U4 W5 U3 U5 T5 W6 V6 U6 T6 W7 V7 U7 T7 W8 V8 U8 T8 W9 V9 T9 U9 V10 U10 T10 W10 U11 T11 V11 W11 T12 U12 V12 Pin Name VssQ A4 VccQ A5 A6 A7 A8 A9 A10 A11 A12 A13 VssQ A14 VccQ A15 A16 A17 A18 A19 A20 A21 Vss Vss A22 Vcc Vcc A23 VssQ A24 VccQ A25 I/O -- O -- O O O O O O O O O -- O -- O O O O O O O -- O O -- -- O -- O -- O Description Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Power supply (0 V) Power supply (0 V) Address bus Power supply (* ) 3 Power supply (* ) Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus 3 Rev. 5.00, 09/03, page 11 of 760 Number of Pins FP-208C FP-208E 87 88 89 90 91 BP-240A W12 T13 U13 V13 W13 Pin Name BS/PTK[4] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTK[6] I/O O / I/O O O O O / I/O Description Bus cycle start signal / input/output port K Read strobe D7-D0 select signal / DQM (SDRAM) D15-D8 select signal / DQM (SDRAM) D23-D16 select signal / DQM (SDRAM) / PCMCIA I/O read / input/output port K D31-D24 select signal / DQM (SDRAM) / PCMCIA I/O write / input/output port K Read/write AUD synchronous / input/output port E Input/output power supply (0 V) Chip select 0/mask ROM chip select 0 Input/output power supply (3.3 V) Chip select 2 / input/output port K Chip select 3 / input/output port K Chip select 4 / input/output port K Chip select 5/CE1 (area 5 PCMCIA) / input/output port K Chip select 6/CE1 (area 6 PCMCIA) CE2 (area 5 PCMCIA) / input/output port E CE2 (area 6 PCMCIA) / input/output port E CK enable (SDRAM) / input/output port K 92 T14 WE3/DQMUU/ICIOWR/ O / I/O PTK[7] RD/WR AUDSYNC/PTE[7] VssQ CS0/MCS[0] VccQ CS2/PTK[0] CS3/PTK[1] CS4/PTK[2] CS5/CE1A/PTK[3] CS6/CE1B CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] O O / I/O -- O -- O / I/O O / I/O O / I/O O / I/O O O / I/O O / I/O O / I/O 93 94 95 96 97 98 99 100 101 102 103 104 105 U14 V14 W14 T15 U15 T16 W15 U16 W16 V15 V17 V16 T18 Rev. 5.00, 09/03, page 12 of 760 Number of Pins FP-208C FP-208E 106 107 108 109 110 111 112 113 114 115 116 117 118 BP-240A U18 U19 R18 T19 T17 R19 U17 R17 R16 P19 P18 P17 P16 Pin Name RAS3L/PTJ[0] PTJ[1] CASL/PTJ[2] VssQ CASU/PTJ[3] VccQ PTJ[4] PTJ[5] DACK0/PTD[5] DACK1/PTD[7] PTE[6] PTE[3] RAS3U/PTE[2] I/O O / I/O O / I/O O / I/O -- O / I/O -- I/O I/O O / I/O O / I/O I/O I/O O / I/O Description Lower 32 M / 64 Mbytes address (SDRAM) RAS / input/output port J 5 Input/output port J* Lower 32 M / 64 Mbytes address (SDRAM) CAS / input/output port J Input/output power supply (0 V) Lower 32 Mbytes address (SDRAM) CAS / input/output port J Input/output power supply (3.3 V) Input/output port J Input/output port J DMA acknowledge 0 / input/output port D DMA acknowledge 1 / input/output port D Input/output port E Input/output port E Upper 32 Mbytes address (SDRAM) RAS / input/output port E Input/output port E Test data output / input/output port E Bus acknowledge Bus request Hardware wait request Manual reset request Analog trigger / input port H IOIS16 (PCMCIA) / input port G ASE mode* / input port G ASE break acknowledge / input port G Input port G / clock output 4 119 120 121 122 123 124 125 126 127 128 129 N19 N18 N17 N16 M19 M18 M17 M16 L19 L18 L16 PTE[1] TDO/PTE[0] BACK BREQ WAIT RESETM ADTRG/PTH[5] IOIS16/PTG[7] ASEMD0/PTG[6] ASEBRKAK/PTG[5] PTG[4]/CK102 I/O O / I/O O I I I I I I O/I I Rev. 5.00, 09/03, page 13 of 760 Number of Pins FP-208C FP-208E 130 131 132 -- 133 134 -- 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 BP-240A L17 K18 K17 K16 K19 J17 J16 J18 J19 H16 H17 H18 H19 G16 G17 G18 G19 F16 F17 F18 F19 E16 E17 D16 E19 D17 Pin Name AUDATA[3]/PTG[3] AUDATA[2]/PTG[2] Vss Vss AUDATA[1]/PTG[1] Vcc Vcc AUDATA[0]/PTG[0] TRST/PTF[7]/PINT[15] TMS/PTF[6]/PINT[14] TDI/PTF[5]/PINT[13] TCK/PTF[4]/PNT[12] IRLS3/PTF[3]/ PINT[11] IRLS2/PTF[2]/ PINT[10] IRLS1/PTF[1]/PINT[9] IRLS0/PTF[0]/PINT[8] MD0 Vcc-PLL1 CAP1 2 Vss-PLL1* 2 Vss-PLL2* I/O I/O / I I/O/I -- -- I/O / I -- -- I/O / I I I I I I I I I I Description AUD data / input port G AUD data / input port G Power supply (0 V) Power supply (0 V) AUD data / input port G Power supply (* ) 3 Power supply (* ) AUD data / input port G Test reset / input port F / port interrupt Test mode switch / input port F / port interrupt Test data input / input port F / port interrupt Test clock / input port F / port interrupt External interrupt request / input port F / port interrupt External interrupt request / input port F / port interrupt External interrupt request / input port F / port interrupt External interrupt request / input port F / port interrupt Clock mode setting PLL1 power supply (* ) PLL1 external capacitance pin PLL1 power supply (0 V) PLL2 power supply (0 V) PLL2 external capacitance pin 3 PLL2 power supply (* ) AUD clock / input port H Power supply (0 V) Power supply (0 V) 3 3 *2 -- -- -- -- -- -- I -- -- CAP2 Vcc-PLL2 Vss Vss *2 AUDCK/PTH[6] Rev. 5.00, 09/03, page 14 of 760 Number of Pins FP-208C FP-208E -- 154 -- 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 -- 174 175 -- BP-240A D19 E18 C19 C18 D18 B16 B17 B15 A16 C16 A15 C17 C15 D15 A14 B14 C14 D14 A13 B13 C13 D13 A12 B12 C12 D12 Pin Name Vss Vcc Vcc XTAL EXTAL STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VssQ CKIO VccQ TxD0/SCPT[0] SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3] TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] Vss Vss RxD2/SCPT[4] Vcc Vcc I/O -- -- -- O I O / I/O O / I/O I/O O -- I/O -- O I/O O I/O O I/O O / I/O I I -- -- I -- -- Description Power supply (0 V) 3 Power supply (* ) Power supply (* ) Clock oscillator pin External clock / crystal oscillator pin Processor status / input/output port J Processor status / input/output port J TMU or RTC clock input/output / input/output port H Interrupt request notification Input/output power supply (0 V) System clock input/output Power supply (3.3 V) Transmit data 0 / SCI output port Serial clock 0 / SCI input/output port Transmit data 1 / SCI output port Serial clock 1 / SCI input/output port Transmit data 2 / SCI output port Serial clock 2 / SCI input/output port Transmit request 2 / SCI input/output port Transmit data 0 / SCI output port Transmit data 1 / SCI output port Power supply (0 V) Power supply (0 V) Transmit data 2 / SCI output port 3 Power supply (* ) Power supply (* ) 3 3 Rev. 5.00, 09/03, page 15 of 760 Number of Pins FP-208C FP-208E 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 BP-240A A11 B11 D11 C11 B10 C10 D10 A10 C9 D9 B9 A9 D8 C8 B8 A8 D7 C7 B7 A7 D6 C6 Pin Name CTS2/IRQ5/SCPT[7] MCS[7]/PTC[7]/PINT[7] MCS[6]/PTC[6]/PINT[6] MCS[5]/PTC[5]/PINT[5] MCS[4]/PTC[4]/PINT[4] VssQ WAKEUP/PTD[3] VccQ RESETOUT/PTD[2] MCS[3]/PTC[3]/PINT[3] MCS[2]/PTC[2]/PINT[2] MCS[1]/PTC[1]/PINT[1] MCS[0]/PTC[0]/PINT[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP CA MD3 MD4 MD5 I/O I Description Transmit clear 2 / external interrupt request / SCI input port O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt -- O / I/O -- O / I/O Input/output power supply (0 V) Standby mode interrupt request notification / input/output port D Input/output power supply (3.3 V) Reset output / input/output port D O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O / I Mask ROM chip select / input/output port C / port interrupt O / I/O O / I/O I I I I I I I DMA request acknowledge / input/output port D DMA request acknowledge / input/output port D DMA request / input port D DMA request / input port D Power-on reset request Chip activate (hardware standby request signal) Area 0 bus width setting Area 0 bus width setting Endian setting Rev. 5.00, 09/03, page 16 of 760 Number of Pins FP-208C FP-208E 198 199 200 201 202 203 204 205 206 207 208 BP-240A B6 A6 D5 C5 D4 A5 C4 A4 B5 B3 B4 Pin Name AVss AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVcc AN[6]/DA[1]/PTL[6] AN[7]/DA[0]/PTL[7] AVss I/O -- I I I I I I -- I I -- Description Analog power supply (0 V) A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L Analog power supply (3.3 V) A/D converter input / D/A converter output / input port L A/D converter input / D/A converter output / input port L Analog power supply (0 V) Notes: 1. Must be connected to the power supply even when the RTC is not used. 2. Except in hardware standby mode, all of the power supply pins must be connected to the system power supply. (Supply power constantly.) In hardware standby mode, power must be supplied at least to VCC -RTC and VSS -RTC. If power is not being supplied to any of the power supply pins other than VCC -RTC and VSS -RTC, hold the CA pin low. 3. 2.0 V for the 200 MHz model, 1.9 V for the 167 MHz model, 1.8 V for the 133 MHz model, 1.7 V for the 100 MHz model. 4. When this LSI is used on the user system alone, without an emulator and the UDI, hold this pin at high level. When this pin is low or open, RESETP may be masked (see section 22, User Debugging Interface (UDI)). 5. B2, B1, C1, U1, V1, W1, V2, W2, W3, W17, W18, W19, V18, V19, B19, A19, B18, A18, A17, A3, A2, and A1 are NC pins. Do not connect anything to these pins. 6. If EXTAL2 is not used, pull this pin up to the Vcc-RTC level. Rev. 5.00, 09/03, page 17 of 760 Rev. 5.00, 09/03, page 18 of 760 Section 2 CPU 2.1 2.1.1 Register Configuration Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7709S normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers--general registers, system registers, and control registers--and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1, the 16 registers comprising BANK1 general registers R0_BANK1- R7_BANK1 and non-banked general registers R8-R15 function as the general register set, with the 8 registers comprising BANK0 general registers R0_BANK0-R7_BANK0 accessed only by the LDC/STC instructions. When the RB bit is 0, BANK0 general registers R0_BANK0-R7_BANK0 and nonbanked general registers R8-R15 function as the general register set, with BANK1 general registers R0_BANK1- R7_BANK1 accessed only by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0-R7_BANK0 and non-banked registers R8-R15 can be accessed as general registers R0-R15, and bank 1 general registers R0_BANK1- R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR) which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), and vector base register (VBR) which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply and accumulate registers (MACL/MACH), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processor mode. The register configuration in each mode is shown in figures 2.1 and 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. Rev. 5.00, 09/03, page 19 of 760 31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR 0 PC User mode register configuration Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. 2. Banked register. Figure 2.1 User Mode Register Configuration Rev. 5.00, 09/03, page 20 of 760 31 R0_BANK1*1 *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1 *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 0 31 R0_BANK0*1 *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1 *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 0 Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBRindirect addressing mode. 2. Banked register When the RB bit of the SR register is 1, the register can be accessed for general use. When the RB bit is 0, it can only be accessed with the LDC/STC instruction. 3. Banked register When the RB bit of the SR register is 0, the register can be accessed for general use. When the RB bit is 1, it can only be accessed with the LDC/STC instruction. a. Privileged mode register configuration (RB = 1) b. Privileged mode register configuration (RB = 0) Figure 2.2 Privileged Mode Register Configuration Rev. 5.00, 09/03, page 21 of 760 Register values after a reset are shown in table 2.1. Table 2.1 Type General registers Control registers Initial Register Values Registers R0 to R15 SR Initial Value* Undefined MD bit = 1, RB bit = 1, BL bit = 1, I3-I0 = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined H'A0000000 GBR, SSR, SPC VBR System registers MACH, MACL, PR PC Note: * Register values are initialized at power-on reset or manual reset. 2.1.2 General Registers There are 16 general registers, designated R0 to R15 (figure 2.3). General registers R0 to R7 are banked registers, with a different R0-R7 register bank (R0_BANK0-R7_BANK0 or R0_BANK1-R7_BANK1) being accessed according to the processor mode. For details, see figures 2.1 and 2.2. The general register configuration is shown in figure 2.3. General Registers 31 R0*1 *2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source register or destination register. 2. R0-R7 are banked registers. In privileged mode, SR.RB specifies which banked registers are accessed as general registers (R0_BANK0-R7_BANK0 or R0_BANK1-R7_BANK1). Figure 2.3 General Registers Rev. 5.00, 09/03, page 22 of 760 2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are four system registers, as follows. * Multiply and accumulate high register (MACH) * Multiply and accumulate low register (MACL) * Procedure register (PR) * Program counter (PC) The system register configuration is shown in figure 2.4. System Registers 31 MACH MACL 0 Multiply and Accumulate High and Low Registers (MACH/L) Store the results of multiply-and-accumulate operations. 0 PR 31 Procedure Register (PR) Stores the return address for exiting a subroutine procedure. Program Counter (PC) Indicates the address four addresses (two instructions) ahead of the currently executing instruction. Initialized to H'A0000000 by a reset. 31 PC 0 Figure 2.4 System Registers 2.1.4 Control Registers Control registers can be accessed in privileged mode using the LDC and STC instructions. The GBR register can also be accessed in user mode. There are five control registers, as follows: * Status register (SR) * Saved status register (SSR) * Saved program counter (SPC) * Global base register (GBR) * Vector base register (VBR) Rev. 5.00, 09/03, page 23 of 760 31 SSR 0 Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. 0 Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling. 0 Global Base Register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. The GBR register can also be accessed in user mode. Its contents are undefined after a reset. 0 Vector Base Register (VBR) Stores base address of exception handling vector area. Initialized to H'0000000 by a reset. 13 12 11 10 9 8 7 3 31 SPC 31 GBR 31 VBR 31 30 29 28 27 1 0 Status 0 MD RB BL 0----------------------0 CL 0 0 M Q I3 I2 I1 I0 0 0 S T register (SR) MD: Processor operation mode bit: Indicates the processor operation mode as follows: MD =1: Privileged mode; MD = 0: User mode MD is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. RB: Register bank bit: Determines the bank of general registers R0-R7 used in processing mode. RB = 1: R0_BANK1-R7_BANK1 and R8-R15 are general registers, and R0_BANK0- R7_BANK0 can be accessed by LDC/STC instructions. RB = 0: R0_BANK0-R7_BANK0 and R8-R15 are general registers, and R0_BANK1- R7_BANK1 can be accessed by LDC/STC instructions. RB is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. BL: Block bit BL = 1: Exceptions and interrupts are suppressed. See section 4, Exception Handling, for details. BL = 0: Exceptions and interrupts are accepted. BL is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. CL: Cache lock bit When set to 1, the cache lock function can be used. M and Q bits: Used by the DIV0S/U and DIV1 instructions. I3-I0 bits: Interrupt mask bits: 4-bit field indicating the interrupt request mask level. I3-I0 do not change to the interrupt acceptance level when an interrupt is generated. Initialized to B'1111 by a reset. S bit: Used by the MAC instruction. T bit: Used by the MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT, and DT instructions to indicate true (1) or false (0). Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L, and ROTCR/L instructions to indicate a carry, borrow, overflow, or underflow. 0 bits: These bits always read 0, and the write value should always be 0. Note: The M, Q, S, and T bits can be set or cleared by special instructions in user mode. Their values are undefined after a reset. All other bits can be read or written in privileged mode. Figure 2.5 Register Set Overview, Control Registers Rev. 5.00, 09/03, page 24 of 760 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 Figure 2.6 Longword 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being stored in a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big-endian or little-endian byte order can be selected for the data format. The endian mode should be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5 pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7. Address A + 1 Address A + 3 Address A + 10 Address A + 8 Address A Address A + 2 Address A + 11 Address A + 9 23 70 23 70 31 15 31 15 Address A Byte0 Byte1 Byte2 Byte3 Byte3 Byte2 Byte1 Byte0 Address A + 4 Word0 Word1 Word1 Word0 Address A + 8 Longword Longword Big-endian mode Little-endian mode Address A + 8 Address A + 4 Address A Figure 2.7 Data Format in Memory Rev. 5.00, 09/03, page 25 of 760 2.3 2.3.1 Instruction Features Execution Environment Data Length: The SH7709S instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords. Literals are sign-extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and zero-extended in logical operations (TST, AND, OR, and XOR instructions). Load/Store Architecture: The SH7709S features a load-store architecture in which basic operations are executed in registers. Operations requiring memory access are executed in registers following register loading, except for bit-manipulation operations such as logical AND functions, which are executed directly in memory. Delayed Branching: Unconditional branching is implemented as delayed branch operations. Pipeline disruptions due to branching are minimized by the execution of the instruction following the delayed branch instruction prior to branching. Conditional branch instructions are of two kinds, delayed and normal. BRA ADD TRGET R1, R0 ;ADD is executed prior to branching to TRGET Rev. 5.00, 09/03, page 26 of 760 T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below. ADD CMP/EQ BT #1, R0 R1, R0 TRGET ;T bit not modified by ADD operation ;T bit set to 1 when R0 = 0 ;branch taken to TRGET when T bit = 1 (R0 = 0) Literals: Byte-length literals are inserted directly into the instruction code as immediate data. To maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in main memory rather than inserted directly into the instruction code. The memory table is accessed by the MOV instruction using PC-relative addressing with displacement, as follows: MOV.W @(disp, PC), R0 Absolute Addresses: As with word and longword literals, absolute addresses must also be stored in a table in main memory. The value of the absolute address is transferred to a register and the operand access is specified by indexed register-indirect addressing, with the absolute address loaded (like word and longword immediate data) during instruction execution. 16-Bit and 32-Bit Displacements: In the same way, 16-bit and 32-bit displacements also must be stored in a table in main memory. Exactly like absolute addresses, the displacement value is transferred to a register and the operand access is specified by indexed register-indirect addressing, loading the displacement (like word and longword immediate data) during instruction execution. Rev. 5.00, 09/03, page 27 of 760 2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Mode Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Calculation Formula -- Rn Register direct Rn Register indirect @Rn Rn Rn Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Register @Rn+ indirect with post-increment Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 1/2/4 + Rn Register @-Rn indirect with pre-decrement Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) Rev. 5.00, 09/03, page 28 of 760 Addressing Mode Register indirect with displacement Instruction Format Effective Address Calculation Method @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Calculation Formula Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Indexed @(R0, Rn) Effective address is sum of register Rn and register indirect R0 contents. Rn + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Rn + R0 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x4 Indexed GBR @(R0, indirect GBR) Effective address is sum of register GBR and R0 contents. GBR + R0 GBR + R0 GBR + R0 Rev. 5.00, 09/03, page 29 of 760 Addressing Mode PC-relative with displacement Instruction Format Effective Address Calculation Method @(disp:8, PC) Effective address is register PC contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC (for longword) & H'FFFFFFFC + disp (zero-extended) x 2/4 PC + disp x 2 or PC&H'FFFFFFFC + disp x 4 Calculation Formula Word: PC + disp x 2 Longword: PC & H'FFFF FFFC + disp x 4 PC-relative disp:8 Effective address is register PC contents with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 PC + disp x 2 disp:12 Effective address is register PC contents with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 PC + disp x 2 Rev. 5.00, 09/03, page 30 of 760 Addressing Mode PC-relative Instruction Format Effective Address Calculation Method Rn Effective address is sum of register PC and Rn contents. PC + R0 PC + R0 Calculation Formula PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. -- -- 8-bit immediate data imm of TRAPA -- instruction is zero-extended and multiplied by 4. Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the IC. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, Rn) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12; PC-relative Rev. 5.00, 09/03, page 31 of 760 2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: mmmm: nnnn: iiii: dddd: Table 2.3 Operation code Source register Destination register Immediate data Displacement Instruction Formats Source Operand 0 xxxx xxxx xxxx xxxx 0 xxxx nnnn xxxx xxxx Instruction Format 0 format 15 n format 15 Destination Operand -- nnnn: register direct nnnn: register direct nnnn: register indirect with pre-decrement Control register or system register Control register or system register -- -- Instruction Example NOP MOVT Rn STS MACH,Rn STC.L SR,@-Rn LDC Rm,SR LDC.L @Rm+,SR JMP BRAF @Rm Rm -- -- Control register or system register Control register or system register m format 15 xxxx mmmm xxxx xxxx 0 mmmm: register direct mmmm: register indirect with postincrement mmmm: register indirect mmmm: PCrelative using Rm Rev. 5.00, 09/03, page 32 of 760 Instruction Format nm format 15 xxxx Source Operand 0 mmmm: register direct nnnn mmmm xxxx Destination Operand nnnn: register direct nnnn: register indirect MACH,MACL Instruction Example ADD Rm,Rn mmmm: register indirect mmmm: register indirect with postincrement (multiply-andaccumulate operation) nnnn: * register indirect with postincrement (multiply-andaccumulate operation) mmmm: register indirect with postincrement mmmm: register direct mmmm: register direct md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: register indirect with displacement 0 R0 (register direct) MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ nnnn: register direct nnnn: register indirect with pre-decrement nnnn: indexed register indirect R0 (register direct) nnnndddd: register indirect with displacement MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0 MOV.B R0,@(disp,Rn) nd4 format 15 xxxx xxxx nnnn dddd Rev. 5.00, 09/03, page 33 of 760 Instruction Format nmd format 15 xxxx Source Operand 0 mmmm: register direct nnnn mmmm dddd Destination Operand nnnndddd: register indirect with displacement nnnn: register direct R0 (register direct) dddddddd: GBR indirect with displacement R0 (register direct) -- -- Instruction Example MOV.L Rm,@(disp,Rn) mmmmdddd: register indirect with displacement d format 15 xxxx xxxx dddd dddd 0 dddddddd: GBR indirect with displacement MOV.L @(disp,Rm),Rn MOV.L @(disp,GBR),R 0 MOV.L R0,@(disp,GBR ) MOVA @(disp,PC),R0 BF label R0 (register direct) dddddddd: PC-relative with displacement dddddddd: PC-relative d12 format 15 xxxx dddd dddd dddd 0 dddddddddddd: PC-relative BRA label (label = disp + PC) MOV.L @(disp,PC),Rn AND.B #imm, @(R0,GBR) AND #imm,R0 TRAPA #imm ADD #imm,Rn nd8 format 15 xxxx nnnn dddd 0 dddddddd: PC-relative with dddd displacement 0 iiiiiiii: immediate iiii nnnn: register direct Indexed GBR indirect R0 (register direct) -- nnnn: register direct i format 15 xxxx xxxx iiii iiiiiiii: immediate iiiiiiii: immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: immediate Note: * In a multiply-and-accumulate instruction, nnnn is the source register. Rev. 5.00, 09/03, page 34 of 760 2.4 2.4.1 Instruction Set Instruction Set Classified by Function The SH7709S instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation Code MOV MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC Function Data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate operation, double-precision multiply-and-accumulate operation 33 No. of Instructions 39 Classification Types Data transfer 5 Rev. 5.00, 09/03, page 35 of 760 Classification Types Arithmetic operations (cont) 21 Operation Code Function MUL MULS MULU NEG NEGC SUB SUBC SUBV Double-precision multiplication (32 x 32 bits) Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow check Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Dynamic arithmetic shift Dynamic logical shift No. of Instructions 33 Logic operations 6 AND NOT OR TAS TST XOR 14 Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD 16 Rev. 5.00, 09/03, page 36 of 760 Classification Types Branch 9 Operation Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure MAC register clear Clear T bit Clear S bit Load to control register Load to system register Load PTE to TLB No operation Prefetch data to cache Return from exception handling Set S bit Set T bit Shift to power-down mode Store from control register Store from system register Trap exception handling No. of Instructions 11 System control 15 CLRMAC CLRT CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA 75 Total: 68 188 Rev. 5.00, 09/03, page 37 of 760 Table 2.5 lists the SH7709S instruction code formats. Table 2.5 Item Instruction mnemonic Instruction Code Format Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ........... 1111: R15 iiii: Immediate data dddd: Displacement* Direction of transfer Memory operand Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit shift Indicates whether privileged mode applies Value when no wait states are inserted The execution cycles listed in the table are minimums. The actual number of cycles may be increased in cases such as the followsing: 1. When contention occurs between instruction fetches and data access 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same Instruction code MSB LSB Operation summary , (xx) M/Q/T & | ^ ~ < Privileged mode Execution cycles T bit Value of T bit after instruction is executed --: No change Note: * Scaling (x1, x2, x4) is performed according to the instruction operand size. Rev. 5.00, 09/03, page 38 of 760 Table 2.6 lists the SH7709S data transfer instructions Table 2.6 Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Data Transfer Instructions Operation imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn, Rm + 1 Rm (Rm) Sign extension Rn, Rm + 2 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Rm) Rn,Rm + 4 Rm 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Rev. 5.00, 09/03, page 39 of 760 Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R0,@(disp,GBR) R0 (disp + GBR) R0,@(disp,GBR) R0 (disp x 2 + GBR) R0,@(disp,GBR) R0 (disp x 4 + GBR) @(disp,GBR),R0 (disp + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 2 + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 4 + GBR) R0 @(disp,PC),R0 Rn disp x 4 + PC R0 T Rn Rm Swap the bottom two bytes Rn Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 5.00, 09/03, page 40 of 760 Table 2.7 lists the SH7709S arithmetic instructions. Table 2.7 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PZ CMP/PL Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Arithmetic Instructions Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 CMP/STR Rm,Rn DIV1 DIV0S DIV0U Rm,Rn Rm,Rn Rev. 5.00, 09/03, page 41 of 760 Instruction DMULS.L Rm,Rn Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Code 0011nnnnmmmm1101 Privileged Mode Cycles T Bit -- 2(to 5)* -- DMULU.L Rm,Rn 0011nnnnmmmm0101 -- 2(to 5)* -- DT Rn 0100nnnn00010000 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 -- -- -- -- -- -- 1 1 1 1 1 Comparison result -- -- -- -- EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L @Rm+,@Rn+ Signed operation of (Rn) 0000nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 4 Rn, Rm + 4 Rm, 32 x 32 + 64 64 bits Signed operation of (Rn) 0100nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 2 Rn, Rm + 2 Rm, 16 x 16 + 64 64 bits Rn x Rm MACL, 32 x 32 32 bits Signed operation of Rn x Rm MACL, 16 x 16 32 bits Unsigned operation of Rn x Rm MACL, 16 x 16 32 bits 0000nnnnmmmm0111 0010nnnnmmmm1111 2(to 5)* -- MAC.W @Rm+,@Rn+ -- 2(to 5)* -- MUL.L Rm,Rn -- -- 2(to 5)* -- 1(to 3)* -- MULS.W Rm,Rn MULU.W Rm,Rn 0010nnnnmmmm1110 -- 1(to 3)* -- Rev. 5.00, 09/03, page 42 of 760 Instruction NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Operation 0-Rm Rn 0-Rm-T Rn, Borrow T Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T Code 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Privileged Mode Cycles T Bit -- -- -- -- -- 1 1 1 1 1 -- Borrow -- Borrow Underflow Note: * The normal number of execution cycles is shown. The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction. Rev. 5.00, 09/03, page 43 of 760 Table 2.8 lists the SH7709S logic operation instructions. Table 2.8 Instruction AND AND Rm,Rn #imm,R0 Logic Operation Instructions Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 3 1 1 1 3 3 1 1 3 1 1 3 -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- -- AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) TAS.B @Rn TST TST Rm,Rn #imm,R0 TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Rev. 5.00, 09/03, page 44 of 760 Table 2.9 lists the SH7709S shift instructions. Table 2.9 Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Shift Instructions Operation T Rn MSB LSB Rn T T Rn T T Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Privileged Mode Cycles T Bit -- -- -- -- -- 1 1 1 1 1 MSB LSB MSB LSB -- SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 -- -- -- 1 1 1 MSB LSB -- SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 MSB LSB -- -- -- -- -- -- SHLL16 Rn SHLR16 Rn Rev. 5.00, 09/03, page 45 of 760 Table 2.10 lists the SH7709S branch instructions. Table 2.10 Branch Instructions Instruction BF BF/S label label Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Code 10001011dddddddd 10001111dddddddd Privileged Mode -- -- Cycles 3/1* 2/1* T Bit -- -- BT label 10001001dddddddd -- 3/1* -- BT/S label 10001101dddddddd -- 2/1* -- BRA BRAF BSR BSRF JMP JSR RTS label Rm label Rm @Rm @Rm 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 -- -- -- -- -- -- -- 2 2 2 2 2 2 2 -- -- -- -- -- -- -- Note: * One state when there is no branch. Rev. 5.00, 09/03, page 46 of 760 Table 2.11 lists the SH7709S system control instructions. Table 2.11 System Control Instructions Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK Operation 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm (Rm) R4_BANK, Rm + 4 Rm (Rm) R5_BANK, Rm + 4 Rm Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 0100mmmm11000111 0100mmmm11010111 Privileged Mode Cycles T Bit -- -- -- 1 1 1 5 3 3 3 3 3 3 3 3 3 3 3 3 7 5 5 5 5 5 5 5 5 5 5 -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- -- -- LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK Rev. 5.00, 09/03, page 47 of 760 Instruction LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK LDS LDS LDS Rm,MACH Rm,MACL Rm,PR Operation (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB No operation (Rm) cache Delayed branch, SSR SR, SPC PC 1S 1T Sleep SR Rn GBR Rn VBR Rn SSR Rn SPC Rn R0_BANK Rn R1_BANK Rn R2_BANK Rn R3_BANK Rn R4_BANK Rn R5_BANK Rn R6_BANK Rn R7_BANK Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Code 0100mmmm11100111 0100mmmm11110111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 Privileged Mode Cycles T Bit -- -- -- -- -- -- 5 5 1 1 1 1 1 1 1 1 2 4 1 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR LDTLB NOP PREF RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn @Rm -- -- -- -- -- -- STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn Note: * The number of cycles until the sleep state is entered. Rev. 5.00, 09/03, page 48 of 760 Instruction STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L R0_BANK, @-Rn STC.L R1_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R3_BANK, @-Rn STC.L R4_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R6_BANK, @-Rn STC.L R7_BANK, @-Rn STS STS STS MACH,Rn MACL,Rn PR,Rn Operation Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) Rn-4 Rn, R0_BANK (Rn) Rn-4 Rn, R1_BANK (Rn) Rn-4 Rn, R2_BANK (Rn) Rn-4 Rn, R3_BANK (Rn) Rn-4 Rn, R4_BANK (Rn) Rn-4 Rn, R5_BANK (Rn) Rn-4 Rn, R6_BANK (Rn) Rn-4 Rn, R7_BANK (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC SPC, SR SSR, imm TRA Code 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011 0100nnnn10010011 0100nnnn10100011 0100nnnn10110011 0100nnnn11000011 0100nnnn11010011 0100nnnn11100011 0100nnnn11110011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Privileged Mode Cycles T Bit -- -- -- -- -- -- -- 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn TRAPA #imm Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: * When there is contention between an instruction fetch and data access * When the destination register in a load (memory-to-register) instruction is also used by the next instruction 2. With the addressing modes using displacement (disp) listed below, the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed. This is done to clarify the operation of the chip. For the actual assembler descriptions, refer to the individual assembler notation rules. @ (disp:4, Rn) ; Register-indirect with displacement @ (disp:8, Rn) ; GBR-indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev. 5.00, 09/03, page 49 of 760 2.4.2 Instruction Code Map Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map Instruction Code MSB 0000 Rn 0000 Rn Fx Fx LSB 0000 0001 SR,Rn SPC,Rn R0_BANK,Rn R4_BANK,Rn Rm @Rn Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) SETT SETS DIV0U MOV.L CLRMAC Rm,@(R0,Rn) MUL.L LDTLB Rm,Rn STC STC R1_BANK,Rn R5_BANK,Rn STC STC BRAF R2_BANK,Rn R6_BANK,Rn Rm STC STC R3_BANK,Rn R7_BANK,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn Fx: 0000 MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 0000 Rn 00MD 0010 STC 0000 Rn 01MD 0010 STC 0000 Rn 10MD 0010 STC 0000 Rn 11MD 0010 STC 0000 Rm 00MD 0011 BSRF 0000 Rn 10MD 0011 PREF 0000 Rn Rm 01MD MOV.B 0000 0000 00MD 1000 CLRT 0000 0000 01MD 1000 CLRS 0000 0000 0000 0000 0000 0000 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0001 Rn 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn 0011 Rn 0011 Rn 0011 Rn Fx Fx Fx Fx Fx Fx Fx 1001 NOP 1010 1011 RTS 1000 1001 1010 STS 1011 MACH,Rn SLEEP RTE MOVT STS MACL,Rn STS Rn PR,Rn Rm 11MD MOV.B Rm disp MOV.L @(R0,Rm),Rn MOV.W @(R0,Rm),Rn Rm,@(disp:4,Rn) Rm,@Rn Rm,@-Rn Rm,Rn MOV.W Rm,@Rn MOV.W Rm,@-Rn AND XTRCT Rm,Rn Rm,Rn MOV.L @(R0,Rm),Rn MAC.L @Rm+,@Rn+ Rm 00MD MOV.B Rm 01MD MOV.B Rm 10MD TST MOV.L MOV.L XOR Rm,@Rn Rm,@-Rn Rm,Rn DIV0S OR Rm,Rn Rm,Rn Rm 11MD CMP/STR Rm,Rn Rm 00MD CMP/EQ Rm,Rn Rm 01MD DIV1 Rm 10MD SUB Rm 11MD ADD Rm,Rn Rm,Rn Rm,Rn MULU.W Rm,Rn CMP/HS Rm,Rn MULSW Rm,Rn CMP/GE Rm,Rn CMP/GT Rm,Rn SUBV ADDV Rm,Rn Rm,Rn DMULU.LRm,Rn CMP/HI Rm,Rn SUBC Rm,Rn Rm,Rn DMULS.L Rm,Rn ADDC Rev. 5.00, 09/03, page 50 of 760 Instruction Code MSB 0100 Rn 0100 Rn 0100 Rn Fx Fx Fx LSB 0000 SHLL 0001 SHLR 0010 STS.L Fx: 0000 MD: 00 Rn Rn MACH,@-Rn SR,@-Rn SPC,@-Rn R0_BANK,@-Rn R4_BANK,@-Rn Fx: 0001 MD: 01 DT Rn SHAL SHAR STS.L STC.L Fx: 0010 MD: 10 Rn Rn PR,@-Rn VBR,@-Rn Fx: 0011 to 1111 MD: 11 CMP/PZ Rn STS.L STC.L MACL,@-Rn GBR,@-Rn 0100 Rn 00MD 0011 STC.L 0100 Rn 01MD 0011 STC.L 0100 Rn 10MD 0011 STC.L 0100 Rn 11MD 0011 STC.L 0100 Rn 0100 Rn 0100 Rm Fx Fx Fx 0100 ROTL 0101 ROTR 0110 LDS.L STC.L SSR,@-Rn STC.L STC.L R1_BANK,@-Rn R5_BANK,@-Rn STC.L STC.L ROTCL R2_BANK,@-Rn R6_BANK,@-Rn STC.L STC.L R3_BANK,@-Rn R7_BANK,@-Rn Rn Rn CMP/PL Rn @Rm+,MACL @Rm+,GBR Rn ROTCR Rn LDS.L LDC.L @Rm+,PR @Rm+,VBR LDC.L @Rm+,SSR @Rm+,MACH LDS.L @Rm+,SR @Rm+,SPC @Rm+,R0_BANK LDC.L @Rm+,R4_BANK LDC.L 0100 Rm 00MD 0111 LDC.L 0100 Rm 01MD 0111 LDC.L 0100 Rm 10MD 0111 LDC.L 0100 Rm 11MD 0111 LDC.L 0100 Rn 0100 Rn 0100 Rm 0100 Rm/ Rn 0100 Rn 0100 Rn Fx Fx Fx Fx 1000 SHLL2 1001 SHLR2 1010 LDS 1011 JSR LDC.L @Rm+,R1_BANK LDC.L @Rm+,R2_BANK LDC.L @Rm+,R6_BANK LDC.L @Rm+,R3_BANK @Rm+,R7_BANK @Rm+,R5_BANK LDC.L Rn Rn Rm,MACH @Rm SHLL8 SHLR8 LDS TAS.B Rn Rn Rm,MACL @Rn SHLL16 Rn SHLR16 Rn LDS JMP Rm,PR @Rm Rm 1100 SHAD Rm 1101 SHLD Rm,Rn Rm,Rn Rm,SR Rm,SPC Rm,R0_BANK LDC Rm,R4_BANK LDC @Rm+,@Rn+ @(disp:4,Rm),Rn @Rm,Rn @Rm+,Rn MOV.W @Rm,Rn MOV.W @Rm+,Rn SWAP.W Rm,Rn EXTU.W Rm,Rn MOV.L MOV.L NEGC @Rm,Rn @Rm+,Rn Rm,Rn MOV NOT NEG Rm,Rn Rm,Rn Rm,Rn Rm,R1_BANK Rm,R5_BANK LDC LDC Rm,R2_BANK Rm,R6_BANK LDC LDC Rm,R3_BANK Rm,R7_BANK LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR 0100 Rm 00MD 1110 LDC 0100 Rm 01MD 1110 LDC 0100 Rm 10MD 1110 LDC 0100 Rm 11MD 1110 LDC 0100 Rn 0101 Rn 0110 Rn 0110 Rn 0110 Rn 0110 Rn 0111 Rn Rm 1111 MAC.W Rm disp MOV.L Rm 00MD MOV.B Rm 01MD MOV.B Rm 10MD SWAP.B Rm,Rn Rm 11MD EXTU.B Rm,Rn imm ADD #imm:8,Rn EXTS.B Rm,Rn EXTS.W Rm,Rn Rev. 5.00, 09/03, page 51 of 760 Instruction Code MSB 1000 00MD Rn LSB Fx: 0000 MD: 00 Fx: 0001 MD: 01 MOV.W R0,@(disp:4,Rn) MOV.W @(disp:4,Rm),R0 BT BT/S label:8 label:8 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 disp MOV.B R0,@(disp:4,Rn) disp MOV.B @(disp:4,Rm),R0 CMP/EQ #imm:8,R0 1000 01MD Rm 1000 10MD imm/disp 1000 11MD imm/disp 1001 Rn 1010 1011 disp disp disp BF BF/S label:8 label:8 MOV.W @(DISP:8,PC),RN BRA BSR label:12 label:12 MOV.W R0,@(disp:8,GBR) MOV.W @(disp:8,GBR),R0 AND #imm:8,R0 MOV.L R0,@(disp:8,GBR) MOV.L @(disp:8,GBR),R0 XOR #imm:8,R0 TRAPA #imm:8 1100 00MD imm/disp MOV.B R0,@(disp:8,GBR) MOV.B @(disp:8,GBR),R0 TST #imm:8,R0 1100 01MD disp MOVA @(disp:8,PC),R0 OR #imm:8,R0 1100 10MD 1100 11MD imm imm TST.B #imm:8,@(R0,GBR) MOV.L MOV AND.B #imm:8,@(R0,GBR) XOR.B #imm:8,@(R0,GBR) OR.B #imm:8,@(R0,GBR) 1101 Rn 1110 Rn 1111 Note: disp imm @(disp:8,PC),Rn #imm:8,Rn ************ See the SH-3/SH-3E/SH3-DSP Programming Manual for details. Rev. 5.00, 09/03, page 52 of 760 2.5 2.5.1 Processor States and Processor Modes Processor States The SH7709S has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low. See section 4, Exception Handling, for more information on resets. In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of onchip supporting modules other than the bus state controller (BSC) are initialized. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling. In the case of a reset, the CPU branches to address H'A0000000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC) and the status register (SR) contents are saved in the saved status register (SSR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 4, Exception Processing, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. There are two modes in the power-down state: sleep mode, and standby mode. See section 8, Power-Down Modes, for more information. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.8. Rev. 5.00, 09/03, page 53 of 760 From any state when RESETP = 0 From any state but hardware standby mode when RESETM = 0 Power-on reset state RESETP = 0 Manual reset state Reset state RESETP = 1 RESETM = 1 Exception-handling state Interrupt ce ran lea End of exception st c Exception ue transition eq interrupt sr processing Bu Bus cle requ ara est Bus-released state nce Bus req Program execution state ues t s Bu req u t es Interrupt Bus request Bus request clearance SLEEP instruction with STBY bit cleared SLEEP instruction with STBY bit set Sleep mode Hardware standby mode* Standby mode CA = 1,RESETP=0 Power-down state Note: * The hardware standby mode is entered when the CA pin goes low from any state. Figure 2.8 Processor State Transitions 2.5.2 Processor Modes There are two processor modes: privileged mode and user mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is 0, and privileged mode when the MD bit is 1. When the reset state or exception state is entered, the MD bit is set to 1. When exception handling ends, the MD bit is cleared to 0 and user mode is entered. There are certain registers and bits which can only be accessed in privileged mode. Rev. 5.00, 09/03, page 54 of 760 Section 3 Memory Management Unit (MMU) 3.1 3.1.1 Overview Features The SH7709S has an on-chip memory management unit (MMU) that implements address translation. The SH7709S features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables highspeed translation of virtual addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbytes and 4 kbytes). The access right to virtual address space can be set for privileged and user modes to provide memory protection. 3.1.2 Role of MMU The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. However, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands ((1)). Having the process itself consider this mapping onto physical memory would impose a large burden on the process. To lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory ((2)). In a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. Thus a process only has to consider operation in virtual memory. Mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. Switching of physical memory is carried out via secondary storage, etc. The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously ((3)). If processes running in a TSS had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on the individual processes and so improve efficiency ((4)). In the virtual memory system, virtual memory is allocated to each process. The task of the MMU is to perform efficient mapping of these virtual memory areas onto physical memory. It also has a memory protection feature that prevents one process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may occur that the relevant translation information is not recorded in the MMU, with the result that one process may inadvertently access the virtual memory allocated to another process. In this Rev. 5.00, 09/03, page 55 of 760 case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. This makes it possible for memory management to be performed flexibly by software. The MMU has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. This LSI uses the paging method. In the following text, the SH7709S address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space. Rev. 5.00, 09/03, page 56 of 760 Virtual memory Process 1 Physical memory Process 1 Process 1 Physical memory MMU Physical memory (1) (2) Process 1 Physical memory Process 2 Process 1 Virtual memory MMU Physical memory Process 2 Process 3 Process 3 (3) (4) Figure 3.1 MMU Functions Rev. 5.00, 09/03, page 57 of 760 3.1.3 SH7709S MMU Virtual Address Space: The SH7709S uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. * Privileged Mode In privileged mode, there are five areas, P0-P4. The P0 and P3 areas are mapped onto physical address space in page units, in accordance with address translation table information. Writeback or write-through can be selected for write access by means of a cache control register (CCR) setting. Mapping of the P1 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the P1 area, setting a virtual address MSB (bit 31) to 0 generates the corresponding physical address. P1 area accesses can be cached, and the cache control register (CCR) is set to indicate whether to cache or not. Write-back or write-through mode can be selected. Mapping of the P2 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the P2 area, setting the top three virtual address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. P2 area access cannot be cached. The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and no exceptions such as TLB misses occur. Initialization of MMU control registers, exception handling routines, and the like should be located in the P1 and P2 areas. Routines that require high-speed processing should be placed in the P1 area, since it can be cached. Some peripheral module control registers are located in area 1 of the physical address space. When the physical address space is not used for address translation, these registers should be located in the P2 area. When address translation is to be used, set no caching. The P4 area is used for mapping peripheral module register addresses, etc. * User Mode In user mode, 2 Gbytes of the virtual address space from H'00000000 to H'7FFFFFFF (area U0) can be accessed. U0 is mapped onto physical address space in page units, in accordance with address translation table information. Rev. 5.00, 09/03, page 58 of 760 H'00000000 H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) Area P0 2-Gbyte virtual space, cacheable (write-back/write-through) Area U0 H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) 0.5-Gbyte fixed physical space, non-cacheable 0.5-Gbyte virtual space, cacheable (write-back/write-through) 0.5-Gbyte control space, non-cacheable H'80000000 Area P1 H'A0000000 Area P2 Address error Area P3 H'C0000000 H'E0000000 H'FFFFFFFF Area P4 H'FFFFFFFF Privileged mode User mode Figure 3.2 Virtual Address Space Mapping Physical Address Space: The SH7709S supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller (BSC), for details. Address Translation: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. When an access to an area other than P4 occurs, if the accessed virtual address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely defined. If it belongs to area P0, P3, or U0, the TLB is searched by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The corresponding physical address and the page control information are read from the TLB and the physical address is determined. Rev. 5.00, 09/03, page 59 of 760 If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed. When the MMU is enabled, address translation information that results in a physical address space of H'80000000-H'FFFFFFFF should not be registered in the TLB. When the MMU is disabled, the virtual address is used directly as the physical address. As the SH7709S supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 10, Bus State Controller (BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area, H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical address. When access to these addresses is performed with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. Single or multiple virtual mode is selected by a value set in the MMU control register (MMUCR). In terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the TLB address comparison method (see section 3.3.3, TLB Address Comparison). Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing virtual address space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently running process in the page table entry register high (PTEH) within the MMU. When the process is switched using the ASID, the TLB does not have to be purged. In single virtual memory mode, the ASID is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 3.4.2, MMU Software Management). Rev. 5.00, 09/03, page 60 of 760 3.1.4 Register Configuration A register that has an undefined initial value must be initialized by software. Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Name Page table entry register high Page table entry register low Translation table base register TLB exception address register MMU control register Register Configuration Abbreviation PTEH PTEL TTB TEA MMUCR R/W R/W R/W R/W R/W R/W Size Longword Longword Longword Longword Longword Initial Value*1 Undefined Undefined Undefined Undefined *2 Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 Notes: 1. Initialized by a power-on reset or manual reset. 2. SV bit: undefined Other bits: 0 3.2 Register Description There are five registers for MMU processing. These registers are located in address space area P4 and can only be accessed from privileged mode by specifying the address. 1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address at which the exception is generated in case of an MMU exception or address error exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the ASID, software sets the number of the currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB instruction. 2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified in response to a software command. (Refer to section 3.4.3, MMU Instruction (LDTLB), and section 3.5, MMU Exceptions.) 3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the base address of the current page table. The hardware does not set any value in TTB automatically. TTB is available to software for general purposes. 4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the virtual address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. Rev. 5.00, 09/03, page 61 of 760 5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the P1 or P2 area. The MMU registers are shown in figure 3.3. 31 VPN PTEH 31 29 28 000 31 PPN PTEL TTB TTB 31 Virtual address causing TLB-related or address error exception TEA 31 0 MMUCR 0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be specified in a write to MMUCR only. SV: Single virtual memory mode bit. 0: Multiple virtual memory mode 1: Single virtual memory mode RC: A 2-bit random counter, automatically updated by hardware according to the following rules in the event of an MMU exception. When a TLB miss exception occurs, all TLB entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to RC; if there is one or more invalid way, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB miss exception, the way which caused the exception is set in RC. TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always reads 0. IX: Index mode bit. When 0, VPN bits 16-12 are used as the TLB index number. When 1, the value obtained by EX-ORing ASID bits 4-0 in PTEH and VPN bits 16-12 are used as the TLB index number. AT: Address translation bit. Enables/disables the MMU. 0: MMU disabled 1: MMU enabled Note: * Refer to section 3.3, TLB Functions. 8 7 6543 2 1 0 SV 00 RC 0 TF IX AT 0 10 9 8 7 6 0 V* 0 43210 PR* SZ* C* D* SH* 0 0 10 0 7 ASID 0 Figure 3.3 MMU Register Contents Rev. 5.00, 09/03, page 62 of 760 3.3 3.3.1 TLB Functions Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of virtual addresses and TLB entries. Ways 0-3 Ways 0-3 Entry 0 Entry 1 VPN(31-17) VPN(11-10) ASID(7-0) V Entry 0 PPN(28-10) PR(1-0) SZ C D SH Entry 1 Entry 31 Address array Entry 31 Data array Figure 3.4 Overall Configuration of the TLB Rev. 5.00, 09/03, page 63 of 760 31 VPN 10 9 Offset Virtual address (1-kbyte page) 0 31 VPN 12 11 Offset 0 Virtual address (4-kbyte page) (15) (2) (8) (1) V TLB entry Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16-12 are used as the index number, they are not stored in the TLB entry. ASID: Address space identifier. Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is performed. SH: Share status bit 0 = Page not shared between processes 1 = Page shared between processes SZ: Page-size bit 0 = 1-kbyte page 1 = 4-kbyte page V: Valid bit. Indicates whether entry is valid. 0 = Invalid 1 = Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. PPN: Physical page number. Top 29 bits of physical address. PPN bits 11-10 are not used in case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1-kbyte page (see section 3.4.4, Avoiding Synonym Problems). PR: Set the most significant bit to 0. Protection key field. 2-bit field encoded to define the access rights to the page. 00: Reading only is possible in privileged mode. 01: Reading/writing is possible in privileged mode. 10: Reading only is possible in privileged/user mode. 11: Reading/writing is possible in privileged/user mode. C: Cacheable bit. Indicates whether the page is cacheable. 0: Non-cacheable 1: Cacheable D: Dirty bit. Indicates whether the page has been written to. 0 = Not written to 1 = Written to (19) PPN (2) (1) (1) (1) (1) PR SZ C SH D VPN (31-17) VPN (11-10) ASID Figure 3.5 Virtual Address and TLB Structure Rev. 5.00, 09/03, page 64 of 760 3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16-12 alone are used as the index number 2. When IX = 1, VPN bits 16-12 are EX-ORed with ASID bits 4-0 to generate a 5-bit index number The second method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space (multiple virtual memory) and a specific entry is selected by generating an index number for each process. Figures 3.6 and 3.7 show the indexing schemes. Virtual address 31 17 16 12 11 0 PTEH register 31 VPN 10 0 ASID(4-0) 7 ASID 0 Exclusive-OR Index Ways 0-3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.6 TLB Indexing (IX = 1) Rev. 5.00, 09/03, page 65 of 760 Virtual address 31 17 16 12 11 0 Index Ways 0-3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.7 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered. It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. For example, if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by software. The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page-size information determines whether VPN (11-10) is compared. VPN (11-10) is compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1). Rev. 5.00, 09/03, page 66 of 760 The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 3.8. SH = 1 or (SR.MD = 1 and MMUCR.SV = 1)? Yes No No (4 kbytes) SZ = 0? Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) Bits compared: VPN (31-17) SZ = 0? No (4 kbytes) Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) ASID (7-0) Bits compared: VPN (31-17) ASID (7-0) Figure 3.8 Objects of Address Comparison Rev. 5.00, 09/03, page 67 of 760 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. When the control register in area 1 is mapped, set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 3.2. Table 3.2 Access States Designated by D, C, and PR Bits Privileged Mode Reading D bit 0 1 C bit 0 1 PR bit 00 Permitted Permitted Permitted (no caching) Permitted (with caching) Permitted Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception Permitted Reading Permitted Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception Permitted Permitted User Mode Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception TLB protection violation exception Permitted 01 Permitted 10 11 Permitted Permitted TLB protection violation exception Permitted Rev. 5.00, 09/03, page 68 of 760 3.4 3.4.1 MMU Functions MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit). For details of the determination method and the hardware processing, see section 3.5, MMU Exceptions. 3.4.2 MMU Software Management There are three kinds of MMU software management, as follows. 1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2 for which address translation is not performed. Also, since SV and IX bit changes constitute address translation system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided with software that does not use the MMU. 2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3, MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, Configuration of Memory-Mapped TLB, for details of the memory-mapped TLB. 3. MMU exception processing. When an MMU exception is generated, it is handled on the basis of information set from the hardware side. See section 3.5, MMU Exceptions, for details. When single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to specify recording of all TLB entries. This strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4, Avoiding Synonym Problems. Rev. 5.00, 09/03, page 69 of 760 3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16-12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16-12 specified in PTEH and ASID bits 4-0 in PTEH are used as the index number. Figure 3.9 shows the case where the IX bit in MMUCR is 0. When an MMU exception occurs, the virtual page number of the virtual address that caused the exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception (see figure 3.3). Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception handling routine, TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR. As the LDTLB instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure, therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two instructions after the LDTLB instruction. Rev. 5.00, 09/03, page 70 of 760 MMUCR 31 0 Index 9 0 SV 0 0 RC 0 TF IX AT Way selection PTEL register 31 29 28 10 PTEH register 31 17 VPN 12 10 VPN 8 0 ASID 0 0 0 V 0 PR SZ C D SH 0 000 PPN Write Ways 0 to 3 Write 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.9 Operation of LDTLB Instruction Rev. 5.00, 09/03, page 71 of 760 3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10. To achieve high-speed operation of the SH7709S cache, an index number is created using virtual address bits 11-4. When a 4-kbyte page is used, virtual address bits 11-4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11-4. In cache-based address comparison and recording in the address array, since the cache tag address is a physical address, physical address bits 28-10 are recorded. When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 11-4. However, in case of a 1-kbyte page, virtual address bit (11, 10) is subject to address translation and therefore may not be the same as physical address bit (11, 10). Consequently, the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Virtual address 1 H'00000000 physical address Virtual address 2 H'00000400 physical address H'00000400 H'00000400 Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'C0. Since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical address already used in another TLB entry, it should be recorded in such a way that physical address bit (11, 10) is the same. Note: In readiness for the future expansion of the SuperH RISC engine family, we recommend that, when multiple sets of address translation information are mapped onto the same physical area of memory, you set the VPN numbers so that each VPN [20:10] is equal to the others. We also recommend that you do not map multiple sets of address-translation information that include 1- and 4-kbyte pages to a single physical area. Rev. 5.00, 09/03, page 72 of 760 When using a 4-kbyte page Virtual address 31 VPN 12 11 10 Offset 0 Physical address 31 29 28 PPN 000 12 11 10 Virtual address (11-4) 0 Offset Cache address array Physical address (28-10) When using a 1-kbyte page Virtual address 31 VPN 11 10 9 Offset 0 Physical address 31 29 28 000 PPN 11 10 9 Virtual address (11-4) 0 Offset Cache address array Physical address (28-10) Figure 3.10 Synonym Problem Rev. 5.00, 09/03, page 73 of 760 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception processing includes both hardware and software operations. Hardware Operations: In a TLB miss, the SH7709S hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter (SPC). If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The random counter (RC) field in the MMU control register (MMUCR) is incremented by 1 when all ways are checked for the TLB entry corresponding to the logical address at which the exception occurred, and all ways are valid. If one or more ways are invalid, those ways are set in RC in prioritized order from way 0 through way 1, way 2, and way 3. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000400 to invoke the user-written TLB miss exception handler. Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the value of the physical page number (PPN) field and the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the address translation table in the external memory into the PTEL register in the SH7709S. Rev. 5.00, 09/03, page 74 of 760 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. 3.5.2 TLB Protection Violation Exception A TLB protection violation exception results when the virtual address and the address array of the selected TLB entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the PR field. TLB protection violation exception processing includes both hardware and software operations. Hardware Operations: In a TLB protection violation exception, the SH7709S hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written into SPC (if the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written into SPC). 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that generated the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the TLB protection violation exception handler. Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Rev. 5.00, 09/03, page 75 of 760 3.5.3 TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception processing includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, the SH7709S hardware executes a set of prescribed operations, as follows: 1. The VPN number of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. The way number causing the exception is written to RC in MMUCR. 4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 5. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the delayed branch instruction is written to the SPC. 6. The contents of SR at the time of the exception are written into SSR. 7. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 8. The block (BL) bit in SR is set to 1 to mask any further exception requests. 9. The register bank (RB) bit in SR is set to 1. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100, and the TLB protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: The software searches the page tables in external memory and assigns the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the values of the physical page number (PPN) field and the values of the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the external memory to the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Rev. 5.00, 09/03, page 76 of 760 3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception processing includes both hardware and software operations. Hardware Operations: In an initial page write exception, the SH7709S hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Exception code H'080 is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that caused the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: The software must execute the following operations: 1. Retrieve the required page table entry from external memory. 2. Set the D bit of the page table entry in the external memory to 1. 3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in the external memory to the PTEL register. 4. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Figure 3.11 shows the flowchart for MMU exceptions. Rev. 5.00, 09/03, page 77 of 760 Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? Yes VPNs match? No Yes VPNs and ASIDs match? Yes No TLB invalid exception Privileged mode No No V = 1? TLB miss exception User mode Yes User or privileged? PR check 00/01 W 10 R/W? R 11 R/W? R No D = 1? Yes TLB protection violation exception Initial page write exception No (noncacheable) Memory access C = 1? W W PR check 01/11 R/W? R 00/10 W R/W? R TLB protection violation Yes (cacheable) Cache access Figure 3.11 MMU Exception Generation Flowchart Rev. 5.00, 09/03, page 78 of 760 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in the instruction fetch mode. IF ID EX ID MA EX ID WB MA EX WB MA NOP NOP WB Handler transition processing MMU exception handler IF ID EX MA WB : Exception source stage IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.12 MMU Exception Signals in Instruction Fetch Rev. 5.00, 09/03, page 79 of 760 Figure 3.13 shows the MMU exception signals in the data access mode. IF ID IF EX ID IF MA EX ID WB MA EX ID WB MA EX ID WB MA EX ID WB MA EX WB MA WB NOP NOP Handler transition processing MMU exception handler : Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation IF ID EX MA WB Figure 3.13 MMU Exception Signals in Data Access 3.6 Configuration of Memory-Mapped TLB To allow the management of TLB operations by software, the MOV instruction can be used, in the privileged mode, to read and write TLB contents. The TLB is mapped to the P4 area of the virtual address space. The TLB address array (VPN, V bit, and ASID) is mapped to H'F2000000 to H'F2FFFFFF, and the TLB data array (PPN, PR, SZ, CD, S, and H bits) is mapped to H'F3000000 to H'F3FFFFFF. It is also possible to access the V bits in the address array from the data array. Only longword access is possible, for both the address and data arrays. 3.6.1 Address Array The address array is mapped to H'F2000000 to H'F2FFFFFF. To access the address array, the 32bit address field (for read/write access) and 32-bit data field (for write access) must be specified. The address field has the information that selects the entry to be accessed; the data field specifies the VPN, the V bit, and the ASID to be written to the address array (figure 3.14 (1)). Rev. 5.00, 09/03, page 80 of 760 In the address field, specify VPN in bits 16-12 as the index address that selects the entry, W in bits 9-8 to select the way, and H'F2 in bits 31-24 to indicate access to the address array. Selection of the index address depends on the MMUCR.IX setting. The following 2 types of operations on the address array are possible. (1) Address Array Read Reads VPN, V bit, and ASID from the entry that corresponds to the entry address and way that were specified in the address field. (2) Address Array Write Writes the data set in the data field to the entry that corresponds to the entry address and way that were specified in the address field. 3.6.2 Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. These are specified in the general register. The address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 3.14 (2)). In the address section, specify the entry address for selecting the entry (bits 16-12), W for selecting the way (bits 9-8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and H'F3 to indicate data array access (bits 31-24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. Both reading and writing use the longword of the data array specified by the index address and way number. The access size of the data array is fixed at longword. Rev. 5.00, 09/03, page 81 of 760 (1) TLB Address Array Access Read access 31 Address field 31 Data field VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 0 * * 17 16 0 VPN ** W 0* * 0 ASID 12 11 10 9 8 7 0 VPN 0 V Write access 31 Address field 31 Data field VPN: V: W: VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 VPN 0 * * 17 16 ** W 0* * 0 ASID 12 11 10 9 8 7 * * VPN * V Virtual page number ASID: Address space identifier Valid bit * : Don't care bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data Array Access Read/write access 31 Address field 31 Data field 11110011 29 28 PPN 24 23 17 16 12 11 10 9 8 7 VPN 0 * * ** W * 32 1 * 0 10 9 8 7 6 5 4 000 X V X PR SZ C D SH X PPN: PR: C: SH: VPN: X: W: Physical page number V: Valid bit Protection key field SZ: Page-size bit Cacheable bit D: Dirty bit * : Don't care bit Share status bit Virtual page number 0 for read, don't care bit for write Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access Rev. 5.00, 09/03, page 82 of 760 3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN and ASID within the TLB entry selected by the entry address and data is written to the matching way. If no match is found, there is no operation. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C ; MMUCR.IX=0 ; VPN(31-17)=B'0001 0101 0100 011 VPN(11-10)=B'10 ASID=B'0001 1100 R1=H'F201 3000 ; corresponding entry association is made from the entry selected by ; the VPN(16-12)=B'1 0011 index, the V bit of the hit way is cleared to ; 0,achieving invalidation. MOV.L R0,@R1 Reading the Data of a Specific Entry: This example reads the data section of a specific TLB entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address and the data section of a selected entry is read to R1. ; R1=H'F300 4300 MOV.L @R0,R1 VPN(16-12)=B'00100 Way 3 3.7 Usage Note The operations listed below must only be performed when the TLB is disabled or in the P1 or P2 area. Any subsequent operation that accesses the P0, P3, or U0 area must take place two or more instructions after any of the below operations. 1. Change SR.MD or SR.BL 2. Execute the LDTLB instruction 3. Write to the memory-mapped TLB 4. Change MMUCR. Rev. 5.00, 09/03, page 83 of 760 Rev. 5.00, 09/03, page 84 of 760 Section 4 Exception Handling 4.1 4.1.1 Overview Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction. Here, all exceptions other than resets and interrupts will be called general exceptions. There are thus three types of exceptions: resets, general exceptions, and interrupts. 4.1.2 Register Configuration Table 4.1 lists the registers used for exception handling. A register with an undefined initial value should be initialized by software. Table 4.1 Register TRAPA exception register Exception event register Interrupt event register Interrupt event register2 Register Configuration Abbr. TRA EXPEVT INTEVT R/W R/W R/W R/W Size Longword Longword Longword Longword Initial Value Undefined Address H'FFFFFFD0 Power-on reset: H'000 H'FFFFFFD4 1 Manual reset: H'020* Undefined Undefined H'FFFFFFD8 H'04000000 2 (H'A4000000)* INTEVT2 R Notes: 1. H'000 is set in a power-on reset, and H'020 in a manual reset. 2. When address translation by the MMU does not apply, the address in parentheses should be used. 4.2 4.2.1 Exception Handling Function Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine on completion of the routine, restoring the Rev. 5.00, 09/03, page 85 of 760 contents of PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The contents of PC and SR are saved in SPC and SSR, respectively. 2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The register bank (RB) bit in SR is set to 1. 5. An exception code identifying the exception event is written to bits 11-0 of the exception event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register. 6. Instruction execution jumps to the designated exception vector address to invoke the handler routine. 4.2.2 Exception Vector Addresses The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an offset from the vector base address of H'00000400. The vector address offset for general exception events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is H'00000600. The vector base address is loaded into the vector base register (VBR) by software. The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows the relationship between the vector base address, the vector offset, and the vector table. VBR (Vector base address) + Vector offset H'A000 0000 Vector table Figure 4.1 Vector Table In table 4.2, exceptions and their vector addresses are listed by exception type, instruction completion state, relative acceptance priority, relative order of occurrence within an instruction execution sequence and vector address for exceptions and their vector addresses. Rev. 5.00, 09/03, page 86 of 760 Table 4.2 Exception Event Vectors Exception Vector 1 Priority* Order Address 1 1 1 2 2 2 2 -- -- -- 1 2 3 4 Vector Offset Exception Current Type Instruction Exception Event Reset Aborted Power-on reset Manual reset UDI reset General exception events Aborted CPU address error and retried (instruction access) TLB miss TLB invalid (instruction access) TLB protection violation (instruction access) General illegal instruction exception Illegal slot instruction exception CPU address error (data access) H'A00000000 -- H'A00000000 -- H'A00000000 -- -- -- -- -- H'00000100 H'00000400 H'00000100 H'00000100 2 2 2 5 5 6 7 8 9 10 5 n* -- -- -- -- 2 -- -- -- -- -- -- -- -- -- -- -- -- -- H'00000100 H'00000100 H'00000100 H'00000400 H'00000100 H'00000100 H'00000100 H'00000100 H'00000100 H'00000100 H'00000600 H'00000600 H'00000600 TLB miss (data access 2 not in repeat loop) TLB invalid (data access) 2 TLB protection 2 violation (data access) Initial page write Completed Unconditional trap (TRAPA instruction) User breakpoint trap DMA address error General interrupt requests External hardware interrupt UDI interrupt 2 2 2 2 3 4* Completed Nonmaskable interrupt 3 4* 3 Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest. 2. The user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. For an operand break point, use 11. 3. Use software to specify relative priorities of external hardware interrupts and peripheral module interrupts (see section 6, Interrupt Controller (INTC)). Rev. 5.00, 09/03, page 87 of 760 4.2.3 Acceptance of Exceptions Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. All general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. Three general exception events (reserved instruction code exception, unconditional trap, and slot illegal instruction exception) are detected in the decode stage (ID stage) of different instructions and are mutually exclusive events in the instruction pipeline. They have the same execution priority. Figure 4.2 shows the order of general exception acceptance. Rev. 5.00, 09/03, page 88 of 760 Pipeline Sequence: Instruction n IF ID EX MA WB TLB miss (data access) Instruction n + 1 IF ID EX MA WB TLB miss (instruction access) Instruction n + 2 Detection Order: TLB miss (instruction n+1) IF ID EX MA WB RIE (reserved instruction exception) TLB miss (instruction n) and general illegal instruction exception (instruction n + 2) = simultaneous detection Handling Order: TLB miss (instruction n) 1 Re-execution of instruction n Program Order: TLB miss (instruction n + 1) 2 Re-execution of instruction n + 1 RIE (instruction n + 2) 3 IF ID EX MA WB = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back Figure 4.2 Example of Acceptance Order of General Exceptions All exceptions other than a reset are detected in the pipeline ID stage, and accepted at instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction. A completion type exception detected in a delayed branch Rev. 5.00, 09/03, page 89 of 760 instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers either to the next instruction after a delayed unconditional branch instruction or to the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes Table 4.3 lists the exception codes written to the EXPEVT register (for reset or general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify each specific exception event. Table 4.3 Exception Codes Exception Event Power-on reset Manual reset UDI reset General exception events TLB miss/invalid (read) TLB miss/invalid (write) Initial page write TLB protection violation (read) TLB protection violation (write) CPU address error (read) CPU address error (write) Unconditional trap (TRAPA instruction) Illegal general instruction exception Illegal slot instruction exception User breakpoint trap DMA address error General interrupt requests Nonmaskable interrupt UDI interrupt External hardware interrupts: IRL3-IRL0 = 0000 IRL3-IRL0 = 0001 H'200 H'220 Exception Code H'000 H'020 H'000 H'040 H'060 H'080 H'0A0 H'0C0 H'0E0 H'100 H'160 H'180 H'1A0 H'1E0 H'5C0 H'1C0 H'5E0 Exception Type Reset Rev. 5.00, 09/03, page 90 of 760 Exception Type General interrupt requests (cont) Exception Event External hardware interrupts (cont): IRL3-IRL0 = 0010 IRL3-IRL0 = 0011 IRL3-IRL0 = 0100 IRL3-IRL0 = 0101 IRL3-IRL0 = 0110 IRL3-IRL0 = 0111 IRL3-IRL0 = 1000 IRL3-IRL0 = 1001 IRL3-IRL0 = 1010 IRL3-IRL0 = 1011 IRL3-IRL0 = 1100 IRL3-IRL0 = 1101 IRL3-IRL0 = 1110 Exception Code H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 4.2.5 Exception Request Masks When the BL bit in SR is 0, exceptions and interrupts are accepted. If a general exception event occurs when the BL bit in SR is 1, the CPU's internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (H'A0000000) as for a reset. If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted until the BL bit is cleared to 0 by software. For reentrant exception handling, SPC and SSR must be saved and the BL bit in SR cleared to 0. 4.2.6 Returning from Exception Handling The RTE instruction is used to return from exception handling. When RTE is executed, the SPC value is set in PC, and the SSR value in SR, and the return from exception handling is performed by branching to the SPC address. If SPC and SSR have been saved in external memory, set the BL bit in SR to 1, then restore SPC and SSR, and issue an RTE instruction. Rev. 5.00, 09/03, page 91 of 760 4.3 Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit interrupt exception code or a code indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt source (see tables 6.4 and 6.5). The exception code or interrupt priority code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 3. Interrupt event register 2 (INTEVT2) resides at address H'04000000, and contains a 12-bit exception code. The exception code set in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. 4. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of the EXPEVT, INTEVT, INTEVT2, and TRA registers are shown in figure 4.3. EXPEVT, INTEVT, and INTEVT2 registers 31 0 0: 11 0 0 Exception code Reserved bits, always read as 0 TRA register 31 0 0 9 imm 20 00 imm: 8-bit immediate data in TRAPA instruction Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers Rev. 5.00, 09/03, page 92 of 760 4.4 4.4.1 Exception Handling Operation Reset The reset sequence is used to power up or restart the SH7709S from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately. In the case of a manual reset, however, reset processing is executed after completion of any memory access being executed. The reset sequence consists of the following operations: 1. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The RB bit in SR is set to 1. 4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11- 0 of the EXPEVT register to identify the exception event. 5. Instruction execution jumps to the user-written exception handler at address H'A0000000. 4.4.2 Interrupts An interrupt handling request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: 1. The contents of PC and SR are saved to SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The RB bit in SR is set to 1. 5. An encoded value identifying the exception event is written to bits 11-0 of the INTEVT and INTEVT2 registers. 6. Instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (VBR) and H'00000600 to invoke the exception handler. Rev. 5.00, 09/03, page 93 of 760 4.4.3 General Exceptions When the SH7709S encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of PC and SR are saved to SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The RB bit in SR is set to 1. 5. Instruction execution jumps to the vector location designated by either the sum of the vector base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke the exception handler. 4.5 Individual Exception Operations This section describes the conditions for specific exception handling, and this LSI operations. 4.5.1 Resets * Power-On Reset Conditions: RESETP low Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral modules are initialized. See the register descriptions in the relevant sections for details. A power-on reset must always be performed when powering on. A low level is output from the RESETOUT pin, and a high level is output from the STATUS0 and STATUS1 pins. * Manual Reset Conditions: RESETM low Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral modules are initialized. See the register descriptions in the relevant sections for details. A low level is output from the RESETOUT pin, and a high level is output from the STATUS0 and STATUS1 pins. Rev. 5.00, 09/03, page 94 of 760 * UDI Reset Conditions: UDI reset command input (see section 22.4.3, UDI Reset) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral modules are initialized. See the register descriptions in the relevant sections for details. Table 4.4 Types of Reset Conditions for Transition to Reset State RESETP = Low RESETM = Low UDI reset command input Internal State CPU Initialized Initialized Initialized On-Chip Peripheral Modules (See register configuration in relevant sections) Type Power-on reset Manual reset UDI reset 4.5.2 General Exceptions * TLB miss exception Conditions: Comparison of TLB addresses shows no address match. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. If all ways are valid, 1 is added to the RC bit in MMUCR. If there is one or more invalid way, they are set by priority starting with way 0. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0400. To speed up TLB miss processing, the offset differs from other exceptions. Rev. 5.00, 09/03, page 95 of 760 * TLB invalid exception Conditions: Comparison of TLB addresses shows address match but the TLB entry valid bit (V) is 0. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Initial page write exception Conditions: A hit occurred to the TLB for a store access, but the TLB entry data bit (D) is 0. This occurs for initial writes to the page registered by the load. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bit in MMUCR. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR 00 01 10 11 Privileged mode Only read enabled Read/write enabled Only read enabled Read/write enabled User mode No access No access Only read enabled Read/write enabled Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. Rev. 5.00, 09/03, page 96 of 760 * CPU address error Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF Operations: The virtual address (32 bits) that caused the exception is set in TEA. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing Flow in Event of MMU Exception, for more information. * Unconditional trap Conditions: TRAPA instruction executed Operations: The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC. SR from the time when the TRAPA instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA (9-0). H'160 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Illegal general instruction exception Conditions: a. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'Fxxx b. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access GBR with LDC/STC are not privileged instructions and therefore do not apply. Operations: PC and SR of the instruction that generated this instruction are saved to SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'100. When an undefined code other than H'Fxxx is decoded, operation cannot be guaranteed. Rev. 5.00, 09/03, page 97 of 760 * Illegal slot instruction Conditions: a. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S b. When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR c. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access GBR with LDC/STC are not privileged instructions and therefore do not apply. Operations: PC of the immediately preceding delay branch instruction is saved to SPC. SR of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * User break point trap Conditions: When a break condition set in the user break controller is satisfied Operations: When a post-execution break occurs, PC of the instruction immediately after the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of the instruction that set the break point is set in SPC. SR when the break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller, for more information. * DMA address error Conditions: a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) Operations: PC of the instruction immediately after the instruction executed before the exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. Rev. 5.00, 09/03, page 98 of 760 4.5.3 1. NMI Interrupts -- Conditions: NMI pin edge detection -- Operations: PC after the instruction that receives the interrupt is saved to SPC, and SR at the point the interrupt is accepted is saved to SSR. H'01C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by SR.IMASK and is accepted with top priority when the BL bit in SR is 0. When the BL bit is 1, the interrupt is masked. See section 6, Interrupt Controller (INTC), for more information. 2. IRL Interrupts -- Conditions: The value of the interrupt mask bits in SR is lower than the IRL3-IRL0 level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. -- Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the IRL3-IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as H'200 + [IRL3-IRL0] x H'20. See table 6.5, for the corresponding codes. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in SR.IMASK. See section 6, Interrupt Controller (INTC), for more information. 3. IRQ Pin Interrupts -- Conditions: The IRQ pin is asserted, SR.IMASK is lower than the IRQ priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. -- Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt mask bits in SR. See section 6, Interrupt Controller (INTC), for more information. 4. PINT Pin Interrupts -- Conditions: The PINT pin is asserted, the interrupt mask bits in SR. is lower than the PINT priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. -- Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits of SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt mask bits in SR. See section 6, Interrupt Controller (INTC), for more information. Rev. 5.00, 09/03, page 99 of 760 5. On-Chip Peripheral Interrupts -- Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC, SCI, IrDA, SCIF, A/D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. -- Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC), for more information. 6. UDI Interrupt -- Conditions: An UDI interrupt command is input (see section 22.4.4, UDI Interrupt), SR.IMASK is lower than 15, and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. -- Operations: The PC value after the instruction that accepts the interrupt is saved to SPC. SR at the point the interrupt is accepted is saved to SSR. H'5E0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC), for more information. 4.6 Cautions * Return from exception handling Check the BL bit in SR with software. When SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. Issue an RTE instruction, which sets SPC in PC and SSR in SR, and causes a branch to the SPC address, and return from exception handling. * Operation when exception or interrupt occurs while SR.BL = 1 Interrupt: Acceptance is suppressed until the BL bit in SR is cleared to 0. If there is an interrupt request and the reception conditions are satisfied, the interrupt is accepted after the execution of the instruction that clears the BL bit in SR to 0. In sleep or standby mode, however, the interrupt will be accepted even when the BL bit in SR is 1. Exception: No user break point trap will occur even when the break conditions are met. When one of the other exceptions occurs, a branch is made to the fixed address of the reset (H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are undefined. Differently from general reset processing, the RESETOUT pin is not asserted, and reset status is output from the STATUS0 and STATUS1 pins. Rev. 5.00, 09/03, page 100 of 760 * SPC when exception occurs: The PC saved to SPC when an exception occurs is as shown below: Re-executing-type exceptions: PC of the instruction that caused the exception is set in SPC and re-executed after return from exception handling. If the exception occurred in a delay slot, however, PC of the immediately prior delayed branch instruction is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. Completed-type exceptions and interrupts: PC of the instruction after the one that caused the exception is set in SPC. If the exception was caused by a conditional delayed branch instruction, however, the branch destination PC is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. * Initial register values after reset Undefined registers R0_BANK0/1-R7_BANK0/1, R8-R15, GBR, SPC, SSR, MACH, MACL, PR Initialized registers VBR = H'00000000 SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3-SR.I0 = H'F. Other SR bits are undefined. PC = H'A0000000 * Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not guaranteed in this case. * When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This will be identified as the occurrence of multiple exceptions, and may initiate reset processing. Rev. 5.00, 09/03, page 101 of 760 Rev. 5.00, 09/03, page 102 of 760 Section 5 Cache 5.1 5.1.1 Overview Features The cache specifications are listed in table 5.1. Table 5.1 Parameter Capacity Structure Locking Line size Number of entries Write system Replacement method Cache Specifications Specification 16 kbytes Instruction/data mixed, 4-way set associative Way 2 and way 3 are lockable 16 bytes 256 entries/way P0, P1, P3, U0: Write-back/write-through selectable Least-recently-used (LRU) algorithm 5.1.2 Cache Structure The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 4 kbytes (16 bytes x 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure. Rev. 5.00, 09/03, page 103 of 760 Address array (ways 0-3) Data array (ways 0-3) LRU Entry 0 V U Tag address Entry 1 . . . . . . 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 255 24 (1 + 1 + 22) bits 255 128 (32 x 4) bits LW0-LW3: Longword data 0-3 255 6 bits Figure 5.1 Cache Structure Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31-10) used for comparison during cache searches. In the SH7709S, the top three of 32 physical address bits are used as shadow bits (see section 10, Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11-4) can be registered in the cache. When an entry is registered, the LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way. The way that is to be replaced on a cache miss is determined by the 6-bit LRU. Table 5.2 shows the correspondence between the LRU bits and the way to be replaced when the cache-lock function is not used (when the cache-lock function is used, refer to section 5.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 5.2. Rev. 5.00, 09/03, page 104 of 760 The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU (5-0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 LRU and Way Replacement (When the cache lock function is not used) Way to be Replaced 3 2 1 0 5.1.3 Register Configuration Table 5.3 shows details of the cache control register. Table 5.3 Register Cache control register Cache control register 2 Register Configuration Abbr. CCR CCR2 R/W R/W R/W Initial Value H'00000000 H'00000000 Address H'FFFFFFEC Access Size 32-bit H'040000B0 32-bit (H'A40000B0)* Note: * When address translation by the MMU does not apply, the address in parentheses should be used. 5.2 5.2.1 Register Description Cache Control Register (CCR) The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either writethrough mode or write-back mode). Programs that change the contents of the CCR register should be placed in address space that is not cached. When updating the contents of the CCR register, always set bits 4 to 0. Figure 5.2 shows the configuration of the CCR register. Rev. 5.00, 09/03, page 105 of 760 31 ... ... ... ... ... ... ... ... 6 5 4 3 CF 2 CB 1 WT 0 CE : CF: Reserved bits. Always 0 when reading. Data written here is also always 0. Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads 0. Write-back to external memory is not performed when the cache is flushed. Write-back/write-through switchover bit. Indicates the cache's operating mode for area P1. 1 = write-back mode, 0 = write-through mode. Write-through bit. Indicates the cache's operating mode for area P0, U0, and P3. 1 = write-through mode, 0 = write-back mode. Cache enable bit. Indicates whether the cache function is used. 1 = cache used, 0 = cache not used. CB: WT: CE: Figure 5.2 CCR Register Configuration 5.2.2 Cache Control Register 2 (CCR2) CCR2 is used to control the cache-lock function and is valid only in cache locking mode. Cache locking mode means that the cache lock bit (bit 12) in SR (status register) is set to 1. The cachelock function is invalid in non-cache locking mode (the cache-lock bit is 0). When a prefetch instruction (PREF) is executed in cache locking mode and a cache miss occurs, one line size of data pointed to by Rn is brought to cache according to the setting of bits 9 and 8 (W3LOAD and W3LOCK) and bits 1 and 0 (W2LOAD and W2LOCK) in CCR2. Table 5.4 shows the relationship between the bit setting and way to be replaced when a prefetch instruction is executed. When a prefetch instruction is executed and there is a cache hit, new data is not fetched and an entry which has already been valid is retained. For example, when the cache-lock, W3LOAD, and W3LOCK bits are set to 1 and a prefetch instruction is executed while one line size of data pointed to by Rn is already in way 0, a cache hit occurs and data is not fetched to way 3. When cache is accessed by means of instructions except for a prefetch instruction in cache locking mode, a way that is replaced by the W3LOCK and W2LOCK bits is restricted. Table 5.5 shows the relationship between the bit setting of CCR2 and way to be replaced. The program which modifies the contents of CCR2 must be placed in an address space which does not cache. Figure 5.3 shows the configuration of CCR2. CCR2 is a write-only register; if read, an undefined value will be returned. Rev. 5.00, 09/03, page 106 of 760 31 9 8 7 2 1 0 W3 W3 LOAD LOCK W2 W2 LOAD LOCK W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way2. In all other conditions the prefetched data will be loaded into the way pointed by LRU. W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit. When W3LOCK = 1 & W3LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way3. In all other conditions the prefetched data will be loaded into the way pointed by LRU. Note: W2LOAD and W3LOAD should not be set to high at the same time. --: Reserved bits. Figure 5.3 CCR2 Register Configuration Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be replaced by tables 5.4 to 5.8. Table 5.4 DSP bit 0 1 1 1 1 1 1 *: Don't care Do not set as W3LOAD=1 and also W2LOAD=1 Way Replacement when PREF Instruction Ended Up in a Cache Miss W3LOAD * * * 0 0 0 1 W3LOCK * 0 0 1 1 * 1 W2LOAD * * 0 * 0 1 0 W2LOCK * 0 1 0 1 1 * Way to be replaced Depends on LRU (table 5.2) Depends on LRU (table 5.2) Depends on LRU (table 5.6) Depends on LRU (table 5.7) Depends on LRU (table 5.8) Way 2 Way 3 Rev. 5.00, 09/03, page 107 of 760 Table 5.5 DSP bit 0 1 1 1 1 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss W3LOAD * * * * * W3LOCK * 0 0 1 1 W2LOAD * * * * * W2LOCK * 0 1 0 1 Way to be replaced Depends on LRU (table 5.2) Depends on LRU (table 5.2) Depends on LRU (table 5.6) Depends on LRU (table 5.7) Depends on LRU (table 5.8) *: Don't care Do not set as W3LOAD=1 and also W2LOAD=1 Table 5.6 LRU (5-0) LRU and Way Replacement (when W2LOCK=1) Way to be Replaced 3 1 0 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Table 5.7 LRU (5-0) LRU and Way Replacement (when W3LOCK=1) Way to be Replaced 2 1 0 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 5.8 LRU (5-0) LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) Way to be Replaced 1 0 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 5.00, 09/03, page 108 of 760 5.3 5.3.1 Cache Operation Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 11-4 of the address (virtual) of the access to memory and the address tag of that entry is read. In parallel to reading of the address tag, the virtual address is translated to a physical address in the MMU. The physical address after translation and the physical address read from the address section are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 5.4 shows a hit on way 1. Rev. 5.00, 09/03, page 109 of 760 Virtual address 31 12 11 4 3 210 Entry selection Longword (LW) selection Ways 0-3 Ways 0-3 MMU 0 1 V U Tag address LW0 LW1 LW2 LW3 255 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.4 Cache Search Scheme (Normal Mode) Rev. 5.00, 09/03, page 110 of 760 5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and the V bit is set to 1. 5.3.3 Prefetch Operation Prefetch Hit: The LRU will be updated to correctly indicate the latest way to have been hit. Other contents of the cache will remain unchanged. Neither instructions nor data are transferred to the CPU. Prefetch Miss: Neither instructions nor data are transferred to the CPU, and way replacement takes place as shown in table 5.4. All other action is the same as for a read miss. 5.3.4 Write Access Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is issued. In the write-through mode, the data is written to the cache and an external memory write cycle is issued. Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is shown in table 5.5. When the U bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. After the cache completes its fill cycle, the write-back buffer writes back the entry to the memory. In the write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 5.3.5 Write-Back Buffer When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. During the write back cycles, the cache can be accessed. The write-back buffer can hold one line of the cache data (16 bytes) and its physical address. Figure 5.5 shows the configuration of the write-back buffer. Rev. 5.00, 09/03, page 111 of 760 PA (31-4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31-4): Physical address written to external memory Longword 0-3: The line of cache data to be written to external memory Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is placed in an address space to be cached, the memory allocation cache is manipulated if necessary and a write back should be performed by invalidating the entry. This is also applied to memory shared by the CPU and DMAC in this LSI. 5.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in the privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 Address Array The address array is mapped to H'F0000000 to H'F0FFFFFF. The 32-bit address field (for read/write accessed) and 32-bit data field (for write access) must be specified to access an element of the address array. The address field specifies information that selects the entry to be accessed; the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array (figure 5.6 (1)). In the address field, specify the entry's address in bits 11-4 to select the entry, W in bits 13-12 to select the way, the A bit (bit 3) to specify an associative operation, and H'F0 in bits 31-24 to indicate access to the address array. Settings for the W bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. In the data field, specify the tag address in bits 31-10, LRU in bits 9-4, U bit in bit 1, and V bit in bit 0. The upper 3 bits (bit 31-29) of the tag address must always be 0. Rev. 5.00, 09/03, page 112 of 760 The following three operations on the address array are possible. (1) Address Array Read Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address and way that were specified in the address field. No associative operation will be performed, regardless of the value of the associative bit (the A bit). (2) Address Array Write (without Associative Operation) Writes the tag address, LRU, U bit, and V bit specified in the data field to the entry that corresponds to the entry address and way that were specified in the address field. The associative bit (A bit) of the address field must be set to 0. An attempt to write to a cache line for which both the U bit and V bit are set results in a write-back for that cache line. The tag address, LRU, U bit, and V bit specified in the data field are then written. Note that, when a 0 is written to the V bit, a 0 should always be written to the U bit of the same entry, too. (3) Address Array Write (with Associative Operation) The associative bit (A bit) in the address field indicates whether the addresses are compared during writing. With the A bit set to 1, all 4 ways for the entry specified in the address field will be compared to the tag address specified in the data field for a match. The values of the U bit and V bit specified in the data field will be written to the way that has a hit. However, the tag address and the LRU will not be changed. If no way receives a hit, writing does not take place and the result is no operation. This operation is used to invalidate the address specification for a cache. Write back will take place when the U bit of the entry that received a hit is 1. Note that, when a 0 is written to the V bit, a 0 should always be written to the U bit of the same entry, too. 5.4.2 Data Array The address array is mapped to H'F1000000 to H'F1FFFFFF. To access an element of the data array, the 32-bit address field (for read/write access) and 32-bit data field (for write access) must be specified. The address field specifies the information that selects the entry to be accessed; the data field specifies the longword data to be written to the data array. In the address field, specify the entry's address in bits 11-4, L in bits 3-2 to indicate the longword's position within a line (which consists of 16 bytes), W in bits 13-12 to select the way, and H'F1 in bits 31-24 to indicate access to the data array. The L bits (3-2) specification is in the following form: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3. Settings for the W bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. Since access is not allowed crossing longword boundaries, always set 00 in bits 1-0 of the address field. Rev. 5.00, 09/03, page 113 of 760 The following two operations on the data array are possible. Note that these operations will not change the information in the address array. (1) Data Array Read Reads the data at the position selected by the L bits (3-2) of the address field from the entry that corresponds to the entry address and way that were specified in the address field. (2) Data Array Write Writes the longword data set in the data field into the entry that corresponds to the entry address and way that were specified in the address field. The longword data will be written to the entry at the position selected by the L bits (3-2) of the address field. 1. Address array access Address specification Read access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 *............* W Entry address 0 * * * Write access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 *............* W Entry address A * * * Data specification (both read and write accesses) 31 30 29 10 9 4 3 2 1 0 000 Address tag (28-10) LRU X X U V 2. Data array access (both read and write accesses) Address specification 31 24 23 14 13 12 11 4 3 2 1 0 1111 0001 *............* W Entry address L 0 0 Data specification 31 0 Longword X: 0 for read, don't care for write *: Don't care bit Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access Rev. 5.00, 09/03, page 114 of 760 5.4.3 Examples of Usage (1) Invalidating a Specific Entry A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry's U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to. In the following example, the write data is specified in R0 and the address is specified in R1. ; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0 ; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0 ; MOV.L R0, @R1 To invalidate all entries and ways, write 0 to the following addresses. Addresses F000 0000 F000 0010 F000 0020 : F000 3FF0 This involves a total of 1,024 writes. The above operation should be performed using a non-cacheable area. (2) Invalidating a Specific Address A specific address can be invalidated by writing a 0 to the entry's U and V bits. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address. If the tag addresses match, data is written to the memory at that address. If no match is found, no operation is carried out. If the entry's U bit is 1 at that time, the entry is written back. ; R0 = H'0110 0010; Tag address = B'0000 0001 0001 0000 0000 00, U = 0, V=0 ; R1 = H'F000 0088; Address array access, Entry = H'08, A = 1 ; MOV.L R0, @R1 Rev. 5.00, 09/03, page 115 of 760 In the following example, an address (32-bit) to be purged is specified in R0. MOV.L #H'00000FF0, R1 AND R0, R1 ; ; The entry address is fetched. ; ; The start is set to H'F0 and the A bit to 1. MOV.L #H'1FFFFC00, R3 AND R0, R3 ; ; The tag address is fetched. U = V = 0. ; Associative purge. MOV.L #H'F0000008, R2 OR R1, R2 MOV.L R3, @R2 The above operation should be performed using a non-cacheable area. (3) Reading Data from a Specific Entry This example reads the data section of a specific entry. The longword in the data field of the data array in figure 5.6 is read to the register. ; R0 = H'F100 004C; Data array access, Entry = H'04, ; Way = 0, Longword address = 3 ; MOV.L R0, @R1 ; Longword 3 is read. Rev. 5.00, 09/03, page 116 of 760 Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1.1 Features The INTC has the following features: * 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the priorities of on-chip peripheral module, IRQ, and PINT interrupts can be selected from 16 levels for individual request sources. * NMI noise canceler function: An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. * External devices can be notified that an interrupt has been received (IRQOUT): When the SH7709S has released the bus, the external bus master can be notified that an external interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred, enabling the bus to be requested. Rev. 5.00, 09/03, page 117 of 760 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRL3-IRL0 IRLS3-IRLS0 IRQ0-IRQ5 PINT0-PINT15 DMAC IrDA SCIF SCI ADC TMU RTC WDT REF UDI 4 4 6 16 Input/output control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request/ refresh request) (Interrupt request) Comparator Priority identifier Interrupt request SR 3210 CPU ICR IPR IPRA-IPRE Internal bus Bus interface Legend : Timer unit TMU : Realtime clock unit RTC : Serial communication interface SCI : Serial communication interface (with IrDA) IrDA : Serial communication interface (with FIFO) SCIF : Watchdog timer WDT : Refresh requests in the bus state controller REF : Interrupt control register ICR IPRA-IPRE : Interrupt priority registers A-E : Status register SR : Direct memory access controller DMAC ADC : Analog-to-digital converter UDI : User-debugging interface INTC Figure 6.1 Block Diagram of INTC Rev. 5.00, 09/03, page 118 of 760 6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Name Nonmaskable interrupt input pin Interrupt input pins INTC Pins Abbreviation NMI I/O I Description Input of interrupt request signal, not maskable by the interrupt mask bits in SR. Input of interrupt request signals, maskable by the interrupt mask bits in SR. Input of port interrupt request signals, maskable by the interrupt mask bits in SR. Output of signal that notifies external devices that an interrupt source or memory refresh has occurred IRQ5-IRQ0 IRL3-IRL0 IRLS3-IRLS0 PINT0-PINT15 I Port interrupt input pins I Bus request output pin IRQOUT O Rev. 5.00, 09/03, page 119 of 760 6.1.4 Register Configuration The INTC has the 12 registers listed in table 6.2. Table 6.2 Name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 PINT interrupt enable register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt request register 0 Interrupt request register 1 Interrupt request register 2 INTC Registers Abbr. ICR0 ICR1 ICR2 PINTER IPRA IPRB IPRC IPRD IPRE IRR0 IRR1 IRR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Initial Value* *2 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'00 1 Address H'FFFFFEE0 Access Size 16 H'04000010 16 3 (H'A4000010)* H'04000012 16 3 (H'A4000012)* H'04000014 16 3 (H'A4000014)* H'FFFFFEE2 H'FFFFFEE4 16 16 H'04000016 16 3 (H'A4000016)* H'04000018 16 3 (H'A4000018)* H'0400001A 16 3 (H'A400001A)* H'04000004 8 3 (H'A4000004)* H'04000006 8 3 (H'A4000006)* H'04000008 8 3 (H'A4000008)* Notes: 1. Initialized by a power-on or manual reset. 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. 3. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 120 of 760 6.2 Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL,PINT, and on-chip peripheral modules. Each interrupt has a priority level (0-16), with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 6.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt control register (ICR1) is 1 or the BL bit in the status register (SR) is 0, NMI interrupts are accepted when the MAI bit in the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either rising or falling edge detection. When the NMIE bit in the ICR0 register is changed, an NMI interrupt is not detected for 20 cycles after changing ICR0. NMIE to avoid a false detection of NMI. NMI interrupt exception handling does not affect the interrupt mask level bits (I3-I0) in the status register (SR). When the BL bit is land the BLMSK bit in the ICR1 register is set to 1 and only NMI interrupts are accepted, the SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to return to the original processing from exception handling initiated prior to the NMI interrupt. Use should therefore be restricted to cases where return is not necessary. It is possible to wake the chip up from the standby state with an NMI interrupt (except when the MAI bit in the ICR1 register is set to 1). 6.2.2 IRQ Interrupts IRQ interrupts are input by level or edge from pins IRQ0-IRQ5. The priority level can be set by interrupt priority registers C-D (IPRC-IPRD) in a range from 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0). Edge input interrupt detection requires input of a pulse width of more than two cycles on a peripheral clock (P) basis. The interrupt mask bits (I3-I0) in the status register (SR) are not affected by IRQ interrupt handling. Rev. 5.00, 09/03, page 121 of 760 Interrupts IRQ4-IRQ0 can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of I3-I0 in the SR register (but only when the RTC 32-kHz oscillator is used). If the IRQ edge is input immediately before the CPU enters the standby mode (during the period between when the CPU executes a SLEEP instruction and when STATUS0 becomes high level), the interrupt may not be detected. However, the interrupt will be accepted correctly if the IRQ edge is re-input after the CPU has entered the standby mode (when STATUS0 is high level). In addition, the interrupt may not be detected if the IRQ edge is input during frequency change processing (WDT count). 6.2.3 IRL Interrupts IRL interrupts are input by level at pins IRL3-IRL0 and IRLS3-IRLS0. IRLS3-IRLS0 are enabled when the IRQLVL bit and IRLSEN bit in interrupt control register 1 (ICR1) are both 1. The priority level is the higher level indicated by pins IRL3-IRL0 and IRLS3-IRLS0. An IRL3- IRL0/IRLS3-IRLS0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 6.2 shows an example of IRL interrupt connection. Table 6.3 shows IRL/IRLS pins and interrupt levels. SH7709S Interrupt request Priority encoder 4 IRL3 to IRL0 IRL3 to IRL0 Interrupt request Priority encoder 4 IRLS3 to IRLS0 IRLS3 to IRLS0 Figure 6.2 Example of IRL Interrupt Connection Rev. 5.00, 09/03, page 122 of 760 Table 6.3 IRL3/ L3/ IRLS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IRL3-IRL0/IRLS3-IRLS0 Pins and Interrupt Levels I I I IRL2/ L2/ IRLS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IRL1/ L1/ IRLS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IRL0/ L0/ IRLS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so that no transient level on the IRL/IRLS pin change is detected. In standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead. Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered until the interrupt is accepted and interrupt handling starts. Correct operation cannot be guaranteed if the level is not maintained. However, the priority level can be changed to a higher one. The interrupt mask bits (I3-I0) in the status register (SR) are not affected by IRL/IRLS interrupt handling. When the interrupt level of the IRL interrupt is higher than the level set by the I3-I0 bits in the SR, the IRL interrupt can be used to recover from standby mode (however, this only applies when the RTC is used for 32-kHz oscillator). Rev. 5.00, 09/03, page 123 of 760 6.2.4 PINT Interrupts PINT interrupts are input by level from pins PINT0-PINT15. The priority level can be set by interrupt priority register D (IPRD) in a range from 0 to 15, in groups of PINT0-PINT7 and PINT8-PINT15. The PINT0/1 interrupt level should be held until the interrupt is accepted and interrupt handling is started. Correct operation cannot be guaranteed if the level is not maintained. The interrupt mask bits (I3-I0) in the status register (SR) are not affected by PINT interrupt handling. PINT0/1 interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of I3-I0 in the SR register (but only when the RTC 32-kHz oscillator is used). 6.2.5 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following ten modules: * Timer unit (TMU) * Realtime clock (RTC) * Serial communication interfaces (SCI, IrDA, SCIF) * Bus state controller (BSC) * Watchdog timer (WDT) * Direct memory access controller (DMAC) * Analog-to-digital converter (ADC) * User-debugging interface (UDI) Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value of the INTEVT or INTEVT2 register as a branch offset. A priority level (from 0 to 15) can be set for each module except UDI by writing to interrupt priority registers A, B, and E (IPRA, IPRB, and IPRE). The priority level of the UDI interrupt is 15 (fixed). The interrupt mask bits (I3-I0) in the status register are not affected by on-chip peripheral module interrupt handling. TMU and RTC interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of I3-I0 in the SR register (but only when the RTC 32-kHz oscillator is used). Rev. 5.00, 09/03, page 124 of 760 6.2.6 Interrupt Exception Handling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the interrupt service routine is common to each interrupt source. This is why, for instance, the value of INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. The priority of the on-chip peripheral module, IRQ, and PINT interrupts is set within priority levels 0-15 as required by using interrupt priority registers A-E (IPRA-IPRE). The priority of the on-chip peripheral module, IRQ, and PINT interrupts is set to 0 by a reset. When the priorities of multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default order shown in tables 6.4 and 6.5. Rev. 5.00, 09/03, page 125 of 760 Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) Interrupt Priority IPR (Bit (Initial Value) Numbers) 16 15 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) -- -- IPRC (3-0) IPRC (7-4) IPRC (11-8) IPRD (3-0) IPRD (7-4) IPRD (11-8) Priority within IPR Default Setting Unit Priority -- -- -- -- -- -- -- -- High Interrupt Source NMI UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 PINT DMAC PINT0-7 PINT8-15 DEI0 DEI1 DEI2 DEI3 IrDA ERI1 RXI1 BRI1 TXI1 SCIF ERI2 RXI2 BRI2 TXI2 ADC TMU0 TMU1 TMU2 ADI TUNI0 TUNI1 TUNI2 TICPI2 H'5E0 (H'5E0) H'200-3C0* (H'600) H'200-3C0* (H'620) H'200-3C0* (H'640) H'200-3C0* (H'660) H'200-3C0* (H'680) H'200-3C0* (H'6A0) H'200-3C0* (H'700) H'200-3C0* (H'720) H'200-3C0* (H'800) H'200-3C0* (H'820) H'200-3C0* (H'840) H'200-3C0* (H'860) H'200-3C0* (H'880) H'200-3C0* (H'8A0) H'200-3C0* (H'8C0) H'200-3C0* (H'8E0) H'200-3C0* (H'900) H'200-3C0* (H'920) H'200-3C0* (H'940) H'200-3C0* (H'960) H'200-3C0* (H'980) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'460 (H'460) IPRC (15-12) -- IPRD (15-12) -- IPRE (15-12) High Low 0-15 (0) IPRE (11-8) High Low 0-15 (0) IPRE (7-4) High Low 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRE (3-0) IPRA (11-8) IPRA (7-4) -- -- High Low Low IPRA (15-12) -- Rev. 5.00, 09/03, page 126 of 760 Interrupt Source RTC ATI PRI CUI SCI ERI RXI TXI TEI WDT REF ITI RCMI ROVI INTEVT Code (INTEVT2 Code) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) Interrupt Priority IPR (Bit (Initial Value) Numbers) 0-15 (0) IPRA (3-0) Priority within IPR Default Setting Unit Priority High Low High 0-15 (0) IPRB (7-4) High Low 0-15 (0) 0-15 (0) IPRB (15-12) -- IPRB (11-8) High Low Low Note: * The code corresponding to an interrupt level shown in table 6.6 is set. Rev. 5.00, 09/03, page 127 of 760 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) H'5E0 (H'5E0) Interrupt Priority IPR (Bit (Initial Value) Numbers) 16 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IPRD (3-0) IPRD (7-4) Priority within IPR Default Setting Unit Priority -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High Interrupt Source NMI UDI IRL *2 IRL(3:0) = 0000 H'200 (H'200) 2 IRL(3:0)* = 0001 H'220 (H'220) 2 IRL(3:0)* = 0010 H'240 (H'240) 2 IRL(3:0)* = 0011 H'260 (H'260) 2 IRL(3:0)* = 0100 H'280 (H'280) 2 IRL(3:0)* = 0101 H'2A0 (H'2A0) 2 IRL(3:0)* = 0110 H'2C0 (H'2C0) 2 IRL(3:0)* = 0111 H'2E0 (H'2E0) 2 IRL(3:0)* = 1000 H'300 (H'300) 2 IRL(3:0)* = 1001 H'320 (H'320) 2 IRL(3:0)* = 1010 H'340 (H'340) 2 IRL(3:0)* = 1011 H'360 (H'360) 2 IRL(3:0)* = 1100 H'380 (H'380) 2 IRL(3:0)* = 1101 H'3A0 (H'3A0) 2 IRL(3:0)* = 1110 H'3C0 (H'3C0) IRQ PINT IRQ4 IRQ5 PINT0-7 PINT8-15 H'200-3C0* (H'680) 0-15 (0) 1 H'200-3C0* (H'6A0) 0-15 (0) 1 H'200-3C0* (H'700) 0-15 (0) 1 H'200-3C0* (H'720) 0-15 (0) 1 H'200-3C0* (H'800) 0-15 (0) 1 IPRD (15-12) -- IPRD (11-8) -- IPRE (15-12) High DMAC DEI0 DEI1 DEI2 DEI3 IrDA ERI1 RXI1 BRI1 TXI1 H'200-3C0* (H'820) 1 H'200-3C0* (H'840) H'200-3C0* (H'860) 1 H'200-3C0* (H'880) 0-15 (0) 1 H'200-3C0* (H'8A0) H'200-3C0* (H'8C0) 1 H'200-3C0* (H'8E0) 1 1 1 Low IPRE (11-8) High Low Low Rev. 5.00, 09/03, page 128 of 760 Interrupt Source SCIF ERI2 RXI2 BRI2 TXI2 ADC ADI TMU0 TUNI0 TMU1 TUNI1 TMU2 TUNI2 TICPI2 RTC ATI PRI CUI SCI ERI RXI TXI TEI WDT REF ITI RCMI ROVI INTEVT Code (INTEVT2 Code) 1 Interrupt Priority IPR (Bit (Initial Value) Numbers) IPRE (7-4) Priority within IPR Default Setting Unit Priority High High H'200-3C0* (H'900) 0-15 (0) 1 H'200-3C0* (H'920) H'200-3C0* (H'940) 1 H'200-3C0* (H'960) H'200-3C0* (H'980) 0-15 (0) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'460 (H'460) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 1 1 Low IPRE (3-0) -- IPRA (15-12) -- IPRA (11-8) -- IPRA (7-4) IPRA (3-0) High Low High Low IPRB (7-4) High Low IPRB (15-12) -- IPRB (11-8) High Low Low Notes: 1. The code corresponding to an interrupt level shown in table 6.6 is set. 2. When IRLS3-IRLS0 are enabled, IRL is the higher level of IRL3-IRL0 and IRLS3- IRLS0. Rev. 5.00, 09/03, page 129 of 760 Table 6.6 Interrupt Levels and INTEVT Codes INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Interrupt level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rev. 5.00, 09/03, page 130 of 760 6.3 6.3.1 INTC Registers Interrupt Priority Registers A to E (IPRA-IPRE) Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W Table 6.7 lists the relationship between the interrupt sources and the IPRA--IPRE bits. Table 6.7 Register IPRA IPRB IPRC IPRD IPRE Interrupt Request Sources and IPRA-IPRE Bits 15 to 12 TMU0 WDT IRQ3 PINT0 to PINT7 DMAC Bits 11 to 8 TMU1 REF IRQ2 PINT8 to PINT15 IrDA Bits 7 to 4 TMU2 SCI0 IRQ1 IRQ5 SCIF Bits 3 to 0 RTC Reserved* IRQ0 IRQ4 ADC Note: * Always read as 0. Only 0 should be written. As shown in table 6.7, on-chip peripheral module, IRQ, or PINT interrupts are assigned to four 4bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA-IPRE to H'0000. Rev. 5.00, 09/03, page 131 of 760 6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 NMIL 0/1* R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 NMIE 0 R/W 0 -- 0 R Note: * 1 when NMI input is high, 0 when NMI input is low. Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high Bit 8--NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt request signal at the NMI pin is detected. Bit 8: NMIE 0 1 Description Interrupt request is detected on falling edge of NMI input Interrupt request is detected on rising edge of NMI input Bits 14 to 9 and 7 to 0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 132 of 760 6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 MAI 0 R/W 7 0 R/W 14 1 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 RW 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W IRQLVL BLMSK IRLSEN IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Bit 15--Mask All Interrupts (MAI): When set to 1, all interrupt requests are masked while a low level is being input to the NMI pin. Masks NMI interrupts in standby mode. Bit 15: MAI 0 1 Description All interrupt requests are not masked when NMI pin is low level All interrupt requests are masked when NMI pin is low level (Initial value) Bit 14--Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3-IRQ0 pins are used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3-IRL0. Bit 14: IRQLVL Description 0 1 Used as four independent interrupt request pins IRQ3-IRQ0 Used as 15-level interrupt pins encoded as IRL3-IRL0 (Initial value) Bit 13--BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit in the SR register is 1. Bit 13: BLMSK Description 0 1 NMI interrupts are masked when BL bit is 1 NMI interrupts are accepted regardless of BL bit setting (Initial value) Rev. 5.00, 09/03, page 133 of 760 Bit 12--IRLS Enable (IRLSEN): Enables pins IRLS3-IRLS0. This bit is valid only when the I IRQLVL bit is 1. Bit 12: IRLSEN Description 0 1 Pins IRLS3-IRLS0 disabled Pins IRLS3-IRLS0 enabled (Initial value) Bits 11 and 10--IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 11: IRQ51S Bit 10: IRQ50S Description 0 0 1 1 0 1 An interrupt request is detected at IRQ5 input falling edge (Initial value) An interrupt request is detected at IRQ5 input rising edge An interrupt request is detected at IRQ5 input low level Reserved Bits 9 and 8--IRQ4 Sense Select (IRQ41S, IRQ40S): Select whether the interrupt signal to the IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 9: IRQ41S 0 Bit 8: IRQ40S 0 1 1 0 1 Description An interrupt request is detected at IRQ4 input falling edge (Initial value) An interrupt request is detected at IRQ4 input rising edge An interrupt request is detected at IRQ4 input low level Reserved Bits 7 and 6--IRQ3 Sense Select (IRQ31S, IRQ30S): Select whether the interrupt signal to the IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 7: IRQ31S 0 Bit 6: IRQ30S 0 1 1 0 1 Description An interrupt request is detected at IRQ3 input falling edge (Initial value) An interrupt request is detected at IRQ3 input rising edge An interrupt request is detected at IRQ3 input low level Reserved Rev. 5.00, 09/03, page 134 of 760 Bits 5 and 4--IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 5: IRQ21S 0 Bit 4: IRQ20S 0 1 1 0 1 Description An interrupt request is detected at IRQ2 input falling edge (Initial value) An interrupt request is detected at IRQ2 input rising edge An interrupt request is detected at IRQ2 input low level Reserved Bits 3 and 2--IRQ1 Sense Select (IRQ11S, IRQ10S): Select whether the interrupt signal to the IRQ1 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 3: IRQ11S 0 Bit 2: IRQ10S 0 1 1 0 1 Description An interrupt request is detected at IRQ1 input falling edge (Initial value) An interrupt request is detected at IRQ1 input rising edge An interrupt request is detected at IRQ1 input low level Reserved Bits 1 and 0--IRQ0 Sense Select (IRQ01S, IRQ00S): Select whether the interrupt signal to the IRQ0 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 1: IRQ01S 0 Bit 0: IRQ00S 0 1 1 0 1 Description An interrupt request is detected at IRQ0 input falling edge (Initial value) An interrupt request is detected at IRQ0 input rising edge An interrupt request is detected at IRQ0 input low level Reserved Rev. 5.00, 09/03, page 135 of 760 6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W PINT15S PINT14S PINT13S PINT14S PINT11S PINT10S PINT9S PINT8S PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S Bits 15 to 0--PINT15 to PINT0 Sense Select (PINT15S to PINT0S): Select whether interrupt request signals to PINT15 to PINT0 are detected at the low level or high level. Bits 15-0: PINT15S to PINT0S 0 1 Description Interrupt requests are detected at low level input to the PINT pin (Initial value) Interrupt requests are detected at high level input to the PINT pin Rev. 5.00, 09/03, page 136 of 760 6.3.5 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Bits 15 to 0--PINT15 to PINT0 Interrupt Enable (PINT15E to PINT0E): Enable or diable interrupt request input to pins PINT15 to PINT0. Bits 15-0: PINT15E to PINT0E 0 1 Description PINT input interrupt requests disabled PINT input interrupt requests enabled (Initial value) When all or some of pins PINT0-PINT15 are not used for interrupt input, bits corresponding to pins not used as interrupt request pins should be cleared to 0. Rev. 5.00, 09/03, page 137 of 760 6.3.6 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 0 R 6 0 R 5 IRQ5R 0 R/W 4 IRQ4R 0 R/W 3 IRQ3R 0 R/W 2 IRQ2R 0 R/W 1 IRQ1R 0 R/W 0 IRQ0R 0 R/W PINT0R PINT1R When clearing an IRQ5R-IRQ0R bit to 0, read the bit while bit set to 1, and then write 0. In this case, 0 should be written only to the bits to be cleared and 1 to the other bits. The contents of the bits to which 1 is written do not change. Bit 7--PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether there is interrupt request input to pins PINT0 to PINT7. Bit 7: PINT0R 0 1 Description No interrupt request to pins PINT0 to PINT7 Interrupt to pins PINT0 to PINT7 (Initial value) Bit 6--PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether there is interrupt request input to pins PINT8 to PINT15. Bit 6: PINT1R 0 1 Description No interrupt request input to pins PINT8 to PINT15 Interrupt request input to pins PINT8 to PINT15 (Initial value) Bit 5--IRQ5 Interrupt Request (IRQ5R): Indicates whether there is interrupt request input to the IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by clearing the IRQ5R bit. Bit 5: IRQ5R 0 1 Description No interrupt request input to IRQ5 pin Interrupt request input to IRQ5 pin (Initial value) Rev. 5.00, 09/03, page 138 of 760 Bit 4--IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R 0 1 Description No interrupt request input to IRQ4 pin Interrupt request input to IRQ4 pin (Initial value) Bit 3--IRQ3 Interrupt Request (IRQ3R): Indicates whether there is interrupt request input to the IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by clearing the IRQ3R bit. Bit 3: IRQ3R 0 1 Description No interrupt request input to IRQ3 pin Interrupt request input to IRQ3 pin (Initial value) Bit 2--IRQ2 Interrupt Request (IRQ2R): Indicates whether there is interrupt request input to the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing the IRQ2R bit. Bit 2: IRQ2R 0 1 Description No interrupt request input to IRQ2 pin Interrupt request input to IRQ2 pin (Initial value) Bit 1--IRQ1 Interrupt Request (IRQ1R): Indicates whether there is interrupt request input to the IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by clearing the IRQ1R bit. Bit 1: IRQ1R 0 1 Description No interrupt request input to IRQ1 pin Interrupt request input to IRQ1 pin (Initial value) Bit 0--IRQ0 Interrupt Request (IRQ0R): Indicates whether there is interrupt request input to the IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by clearing the IRQ0R bit. Bit 0: IRQ0R 0 1 Description No interrupt request input to IRQ0 pin Interrupt request input to IRQ0 pin (Initial value) Rev. 5.00, 09/03, page 139 of 760 6.3.7 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 TXI1R 0 R 6 BRI1R 0 R 5 RXI1R 0 R 4 ERI1R 0 R 3 DEI3R 0 R 2 DEI2R 0 R 1 DEI1R 0 R 0 DEI0R 0 R Bit 7--TXI1 Interrupt Request (TXI1R): Indicates whether a TXI1 (IrDA) interrupt request has been generated. Bit 7: TXI1 0 1 Description TXI1 interrupt request not generated TXI1 interrupt request generated (Initial value) Bit 6--BRI1 Interrupt Request (BRI1R): Indicates whether a BRI1 (IrDA) interrupt request has been generated. Bit 6: BRI1R 0 1 Description BRI1 interrupt request not generated BRI1 interrupt request generated (Initial value) Bit 5--RXI1 Interrupt Request (RXI1R): Indicates whether an RXI1 (IrDA) interrupt request has been generated. Bit 5: RXI1R 0 1 Description RXI1 interrupt request not generated RXI1 interrupt request generated (Initial value) Bit 4--ERI1 Interrupt Request (ERI1R): Indicates whether an ERI1 (IrDA) interrupt request has been generated. Bit 4: ERI1R 0 1 Description ERI1 interrupt request not generated ERI1 interrupt request generated (Initial value) Rev. 5.00, 09/03, page 140 of 760 Bit 3--DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request has been generated. Bit 3: DEI3R 0 1 Description DEI3 interrupt request not generated DEI3 interrupt request generated (Initial value) Bit 2--DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request has been generated. Bit 2: DEI2R 0 1 Description DEI2 interrupt request not generated DEI2 interrupt request generated (Initial value) Bit 1--DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request has been generated. Bit 1: DEI1R 0 1 Description DEI1 interrupt request not generated DEI1 interrupt request generated (Initial value) Bit 0--DEI0 Interrupt Request (DEI0R): Indicates whether a DEI0 (DMAC) interrupt request has been generated. Bit 0: DEI0R 0 1 Description DEI0 interrupt request not generated DEI0 interrupt request generated (Initial value) 6.3.8 Interrupt Request Register 2 (IRR2) IRR2 is an 8-bit read-only register that indicates whether an A/D converter or SCIF interrupt request has been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 ADIR 0 R 3 TXI2R 0 R 2 BRI2R 0 R 1 RXI2R 0 R 0 ERI2R 0 R Rev. 5.00, 09/03, page 141 of 760 Bits 7 to 5--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has been generated. Bit 4: ADIR 0 1 Description ADI interrupt request not generated ADI interrupt request generated (Initial value) Bit 3--TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request has been generated. Bit 3: TXI2R 0 1 Description TXI2 interrupt request not generated TXI2 interrupt request generated (Initial value) Bit 2--BRI2 Interrupt Request (BRI2R): Indicates whether a BRI2 (SCIF) interrupt request has been generated. Bit 2: BRI2R 0 1 Description BRI2 interrupt request not generated BRI2 interrupt request generated (Initial value) Bit 1--RXI2 Interrupt Request (RXI2R): Indicates whether an RXI2 (SCIF) interrupt request has been generated. Bit 1: RXI2R 0 1 Description RXI2 interrupt request not generated RXI2 interrupt request generated (Initial value) Bit 0--ERI2 Interrupt Request (ERI2R): Indicates whether an ERI2 (SCIF) interrupt request has been generated. Bit 0: ERI2R 0 1 Description ERI2 interrupt request not generated ERI2 interrupt request generated (Initial value) Rev. 5.00, 09/03, page 142 of 760 6.4 6.4.1 INTC Operation Interrupt Sequence The sequence of interrupt operations is described below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to E (IPRA to IPRE). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting unit (as indicated in tables 6.4 and 6.5) is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3-I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a low level is output from the IRQOUT pin. 4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in synchronization with the peripheral clock (P). The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with the INTEVT and INTEVT2 register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3-I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7709S. 2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the high level. The level is output without regard to the BL bit. 3. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 6.8 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. Rev. 5.00, 09/03, page 143 of 760 Program execution state ICR1.MAI = 1? No No Yes NMI = low? No Yes Interrupt generated? Yes No ICR1.BLMSK = 1? Yes Yes No NMI? Yes Yes NMI? No No SR.BL= 0 or sleep mode? Level 15 interrupt? Yes IRQOUT = low Set interrupt cause in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bits in SR to 1 Branch to exception handler Yes I3-I0 level 14 or lower? No Yes No Level 14 interrupt? Yes I3-I0 level 13 or lower? No Yes No Level 1 interrupt? Yes I3-I0 level 0? No No I3-I0: Interrupt mask bits in status register (SR) Figure 6.3 Interrupt Operation Flowchart Rev. 5.00, 09/03, page 144 of 760 6.4.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler. 2. Clear the cause of the interrupt in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Figure 6.3 shows a sample interrupt operation flowchart. 6.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 6.8. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until completion of an instruction that clears BL to 0. Rev. 5.00, 09/03, page 145 of 760 Table 6.8 Interrupt Response Time Number of States Item Time for priority decision and SR mask bit comparison NMI IRQ PINT Peripheral Modules Notes 0.5 x Icyc 0.5 x Icyc + 0.5 x Bcyc + 1 x Bcyc + 0.5 x Pcyc + 4.5 x 4 Pcyc* 0.5 x Icyc 0.5 x Icyc + 3.5 x Pcyc + 1.5 x 5 Pcyc* 0.5 x Icyc 6 + 3 x Pcyc* Wait time until end of sequence being executed by CPU X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc Interrupt exception handling is kept waiting until the executing instruction ends. If the number of instruction execution states is S*1, the maximum wait time is: X = S - 1. However, if BL is set to 1 by instruction execution or by an exception, interrupt exception handling is deferred until completion of an instruction that clears BL to 0. If the following instruction masks interrupt exception handling, the handling may be further deferred. 5 x Icyc 5 x Icyc 5 x Icyc 5 x Icyc Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started Rev. 5.00, 09/03, page 146 of 760 Number of States Item Response Total time NMI (5.5 + X) x Icyc + 0.5 x Bcyc + 0.5 x Pcyc IRQ (5.5 + X) x Icyc + 1 x Bcyc + 4.5 x 4 Pcyc* PINT (5.5 + X) x Icyc + 3.5 x 5 Pcyc* Peripheral Modules (5.5 + X) x Icyc + 1.5 5 x Pcyc* (5.5 + X) x Icyc 6 + 3 x Pcyc* 5 6 8.5* /11.5* At 60-MHz (CKIO = 30) operation: 0.13-0.28 s 5 10.5 + S* At 60-MHz (CKIO = 15) operation: *6 16.5 + S 0.26-0.56 s (in case of operand cache-hit) At 60-MHz (CKIO = 15) operation: 0.29-0.59 s (when external memory access is performed with wait = 0) Icyc: Duration of one cycle of internal clock supplied to CPU. Bcyc: Duration of one CKIO cycle. Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules. Notes: 1. S also includes the memory access wait time. The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the memory access is a cache-hit, this requires seven instruction execution cycles. When the external access is performed, the corresponding number of cycles must be added. There are also instructions that perform two external memory accesses; if the external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. The internal clock:CKIO:peripheral clock ratio is 2:1:1. 3. The internal clock:CKIO:peripheral clock ratio is 4:1:1. 4. IRQ mode 5. Modules: TMU, RTC, SCI, WDT, REFC 6. Modules: DMAC, ADC, IrDA, SCIF Notes Minimum 7.5 2 case* Maximum 8.5 + S 3 case* 16.5 12.5 26.5 + S 18.5 + S Rev. 5.00, 09/03, page 147 of 760 Interrupt acceptance 0.5 x Icyc + 0.5 x Bcyc + 2 x Pcyc IRL Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler Start of interrupt handling 5 x Icyc IF ID EX EX EX EX IF IF ID EX IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: Instruction decode: Fetched instruction is decoded. EX: Instruction execution: Data operation and address calculation are performed. Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted Rev. 5.00, 09/03, page 148 of 760 Section 7 User Break Controller 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches. 7.1.1 Features The user break controller has the following features: * The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and, then channel B match with logical AND, but not in the same bus cycle). Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID address. Comparison bits are maskable in 32-bit units, user can easily program it to mask addresses at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc. One of two address buses (CPU address bus (LAB), cache address bus (IAB)) can be selected. Data (only on channel B, 32-bit maskable) One of the two data buses (CPU data bus (LDB), cache data bus (IDB)) can be selected. Bus master: CPU cycle or DMAC cycle Bus cycle: instruction fetch or data access Read/write Operand size: byte, word, or longword * User break is generated upon satisfying break conditions. A user-designed user-break condition exception processing routine can be run. * In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. * Maximum repeat times for the break condition: 212 - 1 times. * Eight pairs of branch source/destination buffers. Rev. 5.00, 09/03, page 149 of 760 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the UBC. Access Control IAB LAB Access comparator MDB BBRA BARA Address comparator BAMRA ASID comparator Channel A BASRA Access comparator BBRB BARB Address comparator BAMRB ASID comparator Data comparator Channel B BASRB BDRB BDMRB BETR BRSR PC Trace BRDR CONTROL BRCR LDB/IDB/ XDB/YDB CPU state signals User break request UBC Location CCN Location Break ASID register B Break data register B Break data mask register B Break execution times register Branch source register Branch destination register Break control register Legend BBRA: BARA: BAMRA: BASRA: BBRB: BARB: BAMRB: Break bus cycle register A Break address register A Break address mask register A Break ASID register A Break bus cycle register B Break address register B Break address mask register B BASRB: BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Figure 7.1 Block Diagram of User Break Controller Rev. 5.00, 09/03, page 150 of 760 7.1.3 Table 7.1 Name Register Configuration Register Configuration Abbr. BARA R/W R/W 1 Initial Value* Address Access Size Location 32 32 16 32 32 16 32 32 32 16 32 32 16 16 UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC CCN CCN Break address register A Break address mask register A Break bus cycle register A Break address register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register Execution count break register Branch source register Branch destination register Break ASID register A Break ASID register B H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'0000 Undefined* 2 Undefined* Undefined Undefined 2 H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFFF9C H'FFFFFFAC H'FFFFFFBC H'FFFFFFE4 H'FFFFFFE8 BAMRA R/W BBRA BARB R/W R/W BAMRB R/W BBRB BDRB BRCR BETR BRSR BRDR BASRA BASRB R/W R/W R/W R/W R R R/W R/W BDMRB R/W Notes: 1. Initialized by power-on reset. Values held in standby state and undefined by manual resets. 2. Bit 31 of BRSR and BRDR (valid flag) is initialized by power-on resets. But other bits are not initialized. Rev. 5.00, 09/03, page 151 of 760 7.2 7.2.1 Register Descriptions Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 BAA31 0 R/W 23 BAA23 0 R/W 15 BAA15 0 R/W 7 BAA7 0 R/W 30 BAA30 0 R/W 22 BAA22 0 R/W 14 BAA14 0 R/W 6 BAA6 0 R/W 29 BAA29 0 R/W 21 BAA21 0 R/W 13 BAA13 0 R/W 5 BAA5 0 R/W 28 BAA28 0 R/W 20 BAA20 0 R/W 12 BAA12 0 R/W 4 BAA4 0 R/W 27 BAA27 0 R/W 19 BAA19 0 R/W 11 BAA11 0 R/W 3 BAA3 0 R/W 26 BAA26 0 R/W 18 BAA18 0 R/W 10 BAA10 0 R/W 2 BAA2 0 R/W 25 BAA25 0 R/W 17 BAA17 0 R/W 9 BAA9 0 R/W 1 BAA1 0 R/W 24 BAA24 0 R/W 16 BAA16 0 R/W 8 BAA8 0 R/W 0 BAA0 0 R/W Bits 31 to 0--Break Address A31 to A0 (BAA31 to BAA0): Stores the address on the LAB or IAB specifying break conditions of channel A. Rev. 5.00, 09/03, page 152 of 760 7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. A power-on reset initializes BAMRA to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R/W 23 0 R/W 15 0 R/W 7 BAMA7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 BAMA6 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 BAMA5 0 R/W 28 0 R/W 20 0 R/W 12 0 R/W 4 BAMA4 0 R/W 27 0 R/W 19 0 R/W 11 0 R/W 3 BAMA3 0 R/W 26 0 R/W 18 0 R/W 10 0 R/W 2 BAMA2 0 R/W 25 0 R/W 17 0 R/W 9 0 R/W 1 BAMA1 0 R/W 24 0 R/W 16 0 R/W 8 BAMA8 0 R/W 0 BAMA0 0 R/W BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 Bits 31 to 0--Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specifies bits masked in the channel A break address bits specified by BARA (BAA31-BAA0). Bits 31 to 0: BAMAn 0 1 n = 31 to 0 Description Break address bit BAAn of channel A is included in the break condition (Initial value) Break address bit BAAn of channel A is masked and is not included in the break condition Rev. 5.00, 09/03, page 153 of 760 7.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. A power-on reset initializes BBRA to H'0000. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 CDA1 0 R/W 14 -- 0 R 6 CDA0 0 R/W 13 -- 0 R 5 IDA1 0 R/W 12 -- 0 R 4 IDA0 0 R/W 11 -- 0 R 3 RWA1 0 R/W 10 -- 0 R 2 RWA0 0 R/W 9 -- 0 R 1 SZA1 0 R/W 8 -- 0 R 0 SZA0 0 R/W Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Bits 7 and 6--CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or DMAC cycle as the bus cycle of the channel A break condition. Bit 7: CDA1 0 * 1 *: Don't care Bit 6: CDA0 0 1 0 Description Condition comparison is not performed The break condition is the CPU cycle The break condition is the DMAC cycle (Initial value) Bits 5 and 4--Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. Bit 5: IDA1 0 1 Bit 4: IDA0 0 1 0 1 Description Condition comparison is not performed The break condition is the instruction fetch cycle The break condition is the data access cycle The break condition is the instruction fetch cycle or data access cycle (Initial value) Rev. 5.00, 09/03, page 154 of 760 Bits 3 and 2--Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 0 1 Bit 2: RWA0 0 1 0 1 Description Condition comparison is not performed The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle (Initial value) Bits 1 and 0--Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle for the channel A break condition. Bit 1: SZA1 0 Bit 0: SZA0 0 1 1 0 1 Description The break condition does not include operand size (Initial value) The break condition is byte access The break condition is word access The break condition is longword access Rev. 5.00, 09/03, page 155 of 760 7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. A power-on reset initializes BARB to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 BAB31 0 R/W 23 BAB23 0 R/W 15 BAB15 0 R/W 7 BAB7 0 R/W 30 BAB30 0 R/W 22 BAB22 0 R/W 14 BAB14 0 R/W 6 BAB6 0 R/W 29 BAB29 0 R/W 21 BAB21 0 R/W 13 BAB13 0 R/W 5 BAB5 0 R/W 28 BAB28 0 R/W 20 BAB20 0 R/W 12 BAB12 0 R/W 4 BAB4 0 R/W 27 BAB27 0 R/W 19 BAB19 0 R/W 11 BAB11 0 R/W 3 BAB3 0 R/W 26 BAB26 0 R/W 18 BAB18 0 R/W 10 BAB10 0 R/W 2 BAB2 0 R/W 25 BAB25 0 R/W 17 BAB17 0 R/W 9 BAB9 0 R/W 1 BAB1 0 R/W 24 BAB24 0 R/W 16 BAB16 0 R/W 8 BAB8 0 R/W 0 BAB0 0 R/W Rev. 5.00, 09/03, page 156 of 760 7.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. A power-on reset initializes BAMRB to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R/W 23 0 R/W 15 0 R/W 7 BAMB7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 BAMB6 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 BAMB5 0 R/W 28 0 R/W 20 0 R/W 12 0 R/W 4 BAMB4 0 R/W 27 0 R/W 19 0 R/W 11 0 R/W 3 BAMB3 0 R/W 26 0 R/W 18 0 R/W 10 0 R/W 2 BAMB2 0 R/W 25 0 R/W 17 0 R/W 9 0 R/W 1 BAMB1 0 R/W 24 0 R/W 16 0 R/W 8 BAMB8 0 R/W 0 BAMB0 0 R/W BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 Bits 31 to 0--Break Address Mask Register B31 to B0 (BAMB31 to BAMB0): Specifies bits masked in the channel B break address bits specified by BARB (BAB31--BAB0). Bits 31 to 0: BAMBn 0 1 n = 31 to 0 Description Break address BABn of channel B is included in the break condition (Initial value) Break address BABn of channel B is masked and is not included in the break condition Rev. 5.00, 09/03, page 157 of 760 7.2.6 Break Data Register B (BDRB) BDRB is a 32-bit read/write register. A power-on reset initializes BDRB to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: 31 BDB31 0 R/W 23 BDB23 0 R/W 15 BDB15 0 R/W 7 BDB7 0 30 BDB30 0 R/W 22 BDB22 0 R/W 14 BDB14 0 R/W 6 BDB6 0 29 BDB29 0 R/W 21 BDB21 0 R/W 13 BDB13 0 R/W 5 BDB5 0 28 BDB28 0 R/W 20 BDB20 0 R/W 12 BDB12 0 R/W 4 BDB4 0 27 BDB27 0 R/W 19 BDB19 0 R/W 11 BDB11 0 R/W 3 BDB3 0 26 BDB26 0 R/W 18 BDB18 0 R/W 10 BDB10 0 R/W 2 BDB2 0 25 BDB25 0 R/W 17 BDB17 0 R/W 9 BDB9 0 R/W 1 BDB1 0 24 BDB24 0 R/W 16 BDB16 0 R/W 8 BDB8 0 R/W 0 BDB0 0 Rev. 5.00, 09/03, page 158 of 760 7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W 28 0 R/W 20 0 R/W 12 0 R/W 4 0 R/W 27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W 25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Bits 31 to 0--Break Data Mask Register B31 to B0 (BDMB31 to BDMB0): Specifies bits in the channel B break data bits specified by BDRB (BDB31--BDB0). Bits 31 to 0: BDMBn 0 1 Description Break data BDBn of channel B is included in the break condition (Initial value) Break data BDBn of channel B is masked and is not included in the break condition n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When a byte size is specified as a break condition, the same-byte data must be set in bits 15 to 8 and bits 7 to 0 in BDRB for the break data. Rev. 5.00, 09/03, page 159 of 760 7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel B. A power-on reset initializes BBRB to H'0000. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 CDB1 0 R/W 14 -- 0 R 6 CDB0 0 R/W 13 -- 0 R 5 IDB1 0 R/W 12 -- 0 R 4 IDB0 0 R/W 11 -- 0 R 3 RWB1 0 R/W 10 -- 0 R 2 RWB0 0 R/W 9 -- 0 R 1 SZB1 0 R/W 8 -- 0 R 0 SZB0 0 R/W Bits 15 to 8--Reserved: These bits are always read as 0. These bits are always read as 0. Bits 7 and 6--CPU Cycle/DMAC Cycle Select B (CDB1, CDB0): Select the CPU cycle or DMAC cycle as the bus cycle of the channel B break condition. Bit 7: CDB1 0 * 1 *: Don't care Bit 6: CDB0 0 1 0 Description Condition comparison is not performed The break condition is the CPU cycle The break condition is the DMAC cycle (Initial value) Bits 5 and 4--Instruction Fetch/Data Access Select B (IDB1, IDB0): Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. Bit 5: IDB1 0 1 Bit 4: IDB0 0 1 0 1 Description Condition comparison is not performed The break condition is the instruction fetch cycle The break condition is the data access cycle The break condition is the instruction fetch cycle or data access cycle (Initial value) Rev. 5.00, 09/03, page 160 of 760 Bits 3 and 2--Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 0 1 Bit 2: RWB0 0 1 0 1 Description Condition comparison is not performed The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle (Initial value) Bits 1 and 0--Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for the channel B break condition. Bit 1: SZB1 0 Bit 0: SZB0 0 1 1 0 1 Description The break condition does not include operand size (Initial value) The break condition is byte access The break condition is word access The break condition is longword access Rev. 5.00, 09/03, page 161 of 760 7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. 6. Enable the ASID check. The break control register (BRCR) is a 32-bit read/write register that has break conditions match flags and bits for setting a variety of break conditions. A power-on reset initializes BRCR to H'00000000. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- 0 R 23 -- 0 R 15 0 R/W 7 DBEB 0 R/W 30 -- 0 R 22 -- 0 R 14 0 R/W 6 PCBB 0 R/W 29 -- 0 R 21 0 R/W 13 0 R/W 5 -- 0 R 28 -- 0 R 20 0 R/W 12 0 R/W 4 -- 0 R 27 -- 0 R 19 -- 0 R 11 0 R/W 3 SEQ 0 R/W 26 -- 0 R 18 -- 0 R 10 PCBA 0 R/W 2 -- 0 R 25 -- 0 R 17 -- 0 R 9 -- 0 R 1 -- 0 R 24 -- 0 R 16 -- 0 R 8 -- 0 R 0 ETBE 0 R/W BASMA BASMB SCMFCA SCMFCB SCMFDA SCMFDB PCTE Bits 31 to 22--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 162 of 760 Bit 21--Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description 0 1 All BASRA bits are included in break condition, ASID is checked (Initial value) No BASRA bits are included in break condition, ASID is not checked Bit 20--Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7ASID0 (BASB7 to BASB0) set in BASRB are masked or not. Bit 20: BASMB Description 0 1 All BASRB bits are included in break condition, ASID is checked (Initial value) No BASRB bits are included in break condition, ASID is not checked Bits 19 to 16--Reserved: These bits are always read as 0. The write value should always be 0. Bit 15--CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 15: SCMFCA 0 1 Description The CPU cycle condition for channel A does not match The CPU cycle condition for channel A matches (Initial value) Bit 14--CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 14: SCMFCB 0 1 Description The CPU cycle condition for channel B does not match The CPU cycle condition for channel B matches (Initial value) Rev. 5.00, 09/03, page 163 of 760 Bit 13--DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 13: SCMFDA 0 1 Description The DMAC cycle condition for channel A does not match The DMAC cycle condition for channel A matches (Initial value) Bit 12--DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 12: SCMFDB 0 1 Description The DMAC cycle condition for channel B does not match The DMAC cycle condition for channel B matches (Initial value) Bit 11--PC Trace Enable (PCTE): Enables PC trace. Bit 11: PCTE 0 1 Description Disables PC trace Enables PC trace (Initial value) Bit 10--PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. Bit 10: PCBA 0 1 Description PC break of channel A is set before instruction execution PC break of channel A is set after instruction execution (Initial value) Bits 9 and 8--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--Data Break Enable B (DBEB): Selects whether or not the data bus condition is included in the break condition of channel B. Bit 7: DBEB 0 1 Description No data bus condition is included in the condition of channel B The data bus condition is included in the condition of channel B (Initial value) Rev. 5.00, 09/03, page 164 of 760 Bit 6--PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB 0 1 Description PC break of channel B is set before instruction execution PC break of channel B is set after instruction execution (Initial value) Bits 5 and 4--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--Sequence Condition Select (SEQ): Selects two conditions of channels A and B as independent or sequential. Bit 3: SEQ 0 1 Description Channels A and B are compared under the independent condition (Initial value) Channels A and B are compared under the sequential condition (channel A, then channel B) Bits 2 and 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--The Number of Execution Times Break Enable (ETBE): Enable the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the BETR register. Bit 0: ETBE 0 1 Description The execution-times break condition is masked on channel B The execution-times break condition is enabled on channel B (Initial value) Rev. 5.00, 09/03, page 165 of 760 7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 12 - 1 times. A power-on reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15-12 are always read as 0 and 0 should always be written in these bits. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 0 R/W 14 -- 0 R 6 0 R/W 13 -- 0 R 5 0 R/W 12 -- 0 R 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 0 R/W 0 R/W 0 0 R/W 11 10 9 8 Rev. 5.00, 09/03, page 166 of 760 7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 SVF 0 R 23 BSA23 * R 15 BSA15 * R 7 BSA7 * R 30 PID2 * R 22 BSA22 * R 14 BSA14 * R 6 BSA6 * R 29 PID1 * R 21 BSA21 * R 13 BSA13 * R 5 BSA5 * R 28 PID0 * R 20 BSA20 * R 12 BSA12 * R 4 BSA4 * R 27 BSA27 * R 19 BSA19 * R 11 BSA11 * R 3 BSA3 * R 26 BSA26 * R 18 BSA18 * R 10 BSA10 * R 2 BSA2 * R 25 BSA25 * R 17 BSA17 * R 9 BSA9 * R 1 BSA1 * R 24 BSA24 * R 16 BSA16 * R 8 BSA8 * R 0 BSA0 * R Note: * Undefined value Bit 31--BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the branch source address can be calculated. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 in reading BRSR. Bit 31: SVF 0 1 Description The value of BRSR register is invalid The value of BRSR register is valid Rev. 5.00, 09/03, page 167 of 760 Bits 30 to 28--Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0-7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: PID Even Odd Description PID indicates the instruction buffer number. PiD+2 indicates the instruction buffer number Bits 27 to 0--Branch Source Address (BSA27 to BSA0): These bits store the last fetched address before branch. 7.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight BRDR registers have queue structure and a stored register is shifted every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 DVF 0 R 23 BDA23 * R 15 BDA15 * R 7 BDA7 * R 30 -- * R 22 BDA22 * R 14 BDA14 * R 6 BDA6 * R 29 -- * R 21 BDA21 * R 13 BDA13 * R 5 BDA5 * R 28 -- * R 20 BDA20 * R 12 BDA12 * R 4 BDA4 * R 27 BDA27 * R 19 BDA19 * R 11 BDA11 * R 3 BDA3 * R 26 BDA26 * R 18 BDA18 * R 10 BDA10 * R 2 BDA2 * R 25 BDA25 * R 17 BDA17 * R 9 BDA9 * R 1 BDA1 * R 24 BDA24 * R 16 BDA16 * R 8 BDA8 * R 0 BDA0 * R Note: * Undefined value Rev. 5.00, 09/03, page 168 of 760 Bit 31--BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading BRDR. Bit 31: DVF 0 1 Description The value of BRDR register is invalid The value of BRDR register is valid Bits 30 to 28--Reserved: These bits are always read as 0. The write value should always be 0. Bits 27 to 0--Branch Destination Address (BDA27 to BDA0): These bits store the first fetched address after branch. 7.2.13 Break ASID Register A (BASRA) Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel A. It is not initialized by resets. Bit: Initial value: R/W: 7 BASA7 * R/W 6 BASA6 * R/W 5 BASA5 * R/W 4 BASA4 * R/W 3 BASA3 * R/W 2 BASA2 * R/W 1 BASA1 * R/W 0 BASA0 * R/W Note: * Undefined value Bits 7 to 0--Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0) that is the channel A break condition. 7.2.14 Break ASID Register B (BASRB) Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel B. It is not initialized by resets. Bit: Initial value: R/W: 7 BASB7 * R/W 6 BASB6 * R/W 5 BASB5 * R/W 4 BASB4 * R/W 3 BASB3 * R/W 2 BASB2 * R/W 1 BASB1 * R/W 0 BASB0 * R/W Note: * Undefined value Bits 7 to 0--Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0) that is the channel B break condition. Rev. 5.00, 09/03, page 169 of 760 7.3 7.3.1 Operation Description Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers (BARA and BARB) and break ASID registers (BASRA and BASRB). The masked addresses are set in the break address mask registers (BAMRA and BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The breaking bus conditions are set in the break bus cycle registers (BBRA and BBRB). Three groups of the BBRA and BBRB (CPU cycle/DMAC cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the BRCR. 2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt controller. The break type will be sent to CPU indicating the instruction fetch, pre/post instruction break, data access break. When conditions match up, the CPU condition match flags (SCMFCA and SCMFCB) and DMAC condition match flags (SCMFDA and SCMFDB) for the respective channels are set. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the CPU, but these two break channel match flags could be both set. 7.3.2 Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delay branch instruction, the break is generated prior to execution of the instruction that then first accepts the break. Meanwhile, the break set for pre-instruction-break on delay slot instruction and postinstruction-break on SLEEP instruction are also prohibited. Rev. 5.00, 09/03, page 170 of 760 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break. 4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored. There is thus no need to set break data for the break of the instruction fetch cycle. 7.3.3 Break by Data Access Cycle 1. The memory cycles in which CPU data access breaks occur are from instructions. 2. The relationship between the data access cycle address and the comparison condition for operand size are listed in table 7.2: Table 7.2 Access Size Longword Word Byte Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31-2 to address bus bits 31-2 Compares break address register bits 31-1 to address bus bits 31-1 Compares break address register bits 31-0 to address bus bits 31-0 This means that when address H'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on B channel: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15-8 and bits 7-0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31-16 of BDRB and BDMRB are ignored. 4. When the DMAC data access is included in the break condition: When the address is included in the break condition on DMAC data access, the operand size of the break bus cycle registers (BBRA and BBRB) should be byte, word or no specified operand size. When the data value is included, select either byte or word. Rev. 5.00, 09/03, page 171 of 760 7.3.4 Sequential Break 1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before channel A break condition matches. When channels A and B condition match at the same time, the sequential break is not issued. 2. In sequential break specification, a logical bus or internal bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied at channel B condition match with BETR = H'0001 after channel A condition match. 7.3.5 Value of Saved Program Counter The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows depending on the type of break. 1. When instruction fetch (before instruction execution) is specified as a break condition: The value of the program counter (PC) saved is the address of the instruction that matches the break condition. The fetched instruction is not executed, and a break occurs before it. 2. When instruction fetch (after instruction execution) is specified as a break condition: The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches. The fetched instruction is executed, and a break occurs before the execution of the next instruction. 3. When data access (address only) is specified as a break condition: The PC value is the address of the instruction to be executed following the instruction that matched the break condition. The instruction that matched the condition is executed and the break occurs before the next instruction is executed. 4. When data access (address + data) is specified as a break condition: The PC value is the start address of the instruction that follows the instruction already executed when break processing started up. When a data value is added to the break conditions, the place where the break will occur cannot be specified exactly. The break will occur before the execution of an instruction fetched around the data access where the break occurred. Rev. 5.00, 09/03, page 172 of 760 7.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR, respectively. The branch address and the pointer, which corresponds to the branch, are included in BRSR. 2. The branch address before branch occurs can be calculated from the address and the pointer stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR), and IA (the instruction address before branch occurs) is as follows: IA = BSA - 2 * PID. Notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. In case of the next figure, the instruction "Exec" executed immediately before branch is calculated by IA = BSA - 2 * PID. However, when branch "branch" has delay slot and the destination address is 4n + 2 address, the address "Dest" which is specified by branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA - 2 * PID is not applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: Exec:branch Dest Dest:instr interrupt Int: interrupt routine If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions in this table are accounted for it. Therefore, the true branch source address is calculated with BSA and PID values stored in BRSR. 3. The branch address before branch occurrence, IA, has different values due to some kinds of branch. a. Branch instruction The branch instruction address b. Interrupt The last instruction executed before interrupt The top address of interrupt routine is stored in BRDR. 4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR, longword access should be used. Also, the PC trace has a trace pointer, which initially points to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of the queues, then push up when next pairs come into the queues. The trace pointer will points to the next branch address to be executed, unless it got push out of the queues. When the branch address has been executed, the trace pointer will shift down to next pair of addresses, until it Rev. 5.00, 09/03, page 173 of 760 (not executed) reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer restart at the bottom of the queues. 7.3.7 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle 1. Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00000404, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) No ASID check is included * Channel B Address: Data: H'00008010, Address mask: H'00000006 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included A user break occurs after an instruction of address H'00000404 is executed or before instructions of adresses H'00008010 to H'00008016 are executed. Rev. 5.00, 09/03, page 174 of 760 2. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: Data: H'0003722E, Address mask: H'00000000, ASID = H'70 H'00000000, Data mask: H'00000000 H'00037226, Address mask: H'00000000, ASID = H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Bus cycle: CPU/instruction fetch (before instruction execution)/read/word An instruction with ASID = H'80 and address H'00037226 is executed, and a user break occurs before an instruction with ASID = H'70 and address H'0003722E is executed. 3. Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word No ASID check is included * Channel B Address: Data: H'00031415, Address mask: H'00000000 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. Rev. 5.00, 09/03, page 175 of 760 4. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: Data: H'0003722E, Address mask: H'00000000, ASID: H'70 H'00000000, Data mask: H'00000000 H'00037226, Address mask: H'00000000, ASID: H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequence condition does not match. Therefore, no user break occurs. 5. Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'00001000, Address mask: H'00000000 H'00000000, Data mask: H'00000000 H'00000500, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs before the fifth instruction execution after instructions of address H'00001000 are executed four times. Rev. 5.00, 09/03, page 176 of 760 6. Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00008404, Address mask: H'00000FFF, ASID: H'80 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) * Channel B Address: Data: H'00008010, Address mask: H'00000006, ASID: H'70 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with ASID = H'80 and address H'00008000 to H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010 to H'00008016 are executed. Break Condition Specified to a CPU Data Access Cycle 1. Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'000ABCDE, Address mask: H'000000FF, ASID: H'70 H'0000A512, Data mask: H'00000000 H'00123456, Address mask: H'00000000 Bus cycle: CPU/data access/read (operand size is not included in the condition) Bus cycle: CPU/data access/write/word On channel A, a user break occurs with ASID = H'80 during longword read to address H'00123454, word read to address H'00123456, or byte read to address H'00123456. On channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Rev. 5.00, 09/03, page 177 of 760 Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications: BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'00055555, Address mask: H'00000000, ASID: H'70 H'00000078, Data mask: H'0000000F H'00314156, Address mask: H'00000000, ASID: H'80 Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition) Bus cycle: DMAC/data access/write/byte On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles. On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in address H'00055555. Rev. 5.00, 09/03, page 178 of 760 7.3.8 Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no condition match occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. b. Since the CPU has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. c. When the bus cycle condition for channel A is specified as a break before execution (PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows. A break is issued and condition match flags in BRCR are set to 1, when the bus cycle conditions both for channels A and B match simultaneously. 4. The change of a UBC register value is executed in MA (memory access) stage. Therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. In order to know the timing UBC register is changed, read the last written register. Instructions after then are valid for the newly written register value. 5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR are read. 6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as follows: a. Break and instruction fetch exceptions: Instruction fetch exception occurs first. b. Break before execution and operand exception: Break before execution occurs first. c. Break after execution and operand exception: Operand exception occurs first. Rev. 5.00, 09/03, page 179 of 760 Rev. 5.00, 09/03, page 180 of 760 Section 8 Power-Down Modes 8.1 Overview In the power-down modes, all CPU and some on-chip peripheral module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes The SH7709S has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, SCIF, and IrDA onchip peripheral modules) 4. Hardware standby mode Table 8.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Rev. 5.00, 09/03, page 181 of 760 Table 8.1 Power-Down Modes State Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR Execute SLEEP instruction with STBY bit set to 1 in STBCR Set MSTP bit to 1 in STBCR CPU RegCPG CPU ister Runs Halts Held On-Chip Memory Held On-Chip Peripheral Modules Pins Run Held External Memory Refresh Canceling Procedure 1. Interrupt 2. Reset Halt*1 Mode Sleep mode Standby mode Halts Halts Held Held Held Selfrefresh 1. Interrupt 2. Reset Module standby function Runs Runs Held or halts Halts Halts Held Held Specified module halts Halt*3 *2 Refresh 1. Clear MSTP bit to 0 2. Reset Hardware Drive CA pin low standby mode Held Held Selfrefresh Power-on reset Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 13, Realtime Clock (RTC)). The TMU still runs when output of the RTC is used as input to its counter (see section 12, Timer (TMU)). 2. Depends on the on-chip peripheral module. TMU external pin: Held SCI external pin: Reset 3. The RTC still runs if the START bit in RCR2 is set to 1. The TMU does not run. Rev. 5.00, 09/03, page 182 of 760 8.1.2 Pin Configuration Table 8.2 lists the pins used for the power-down modes. Table 8.2 Pin Name Processing state 1 Processing state 0 Wakeup from standby mode Pin Configuration Abbreviation STATUS1 STATUS0 WAKEUP O I/O O Description Operating state of the processor. HH: Reset, HL: Sleep mode, LH: Standby mode, LL: Normal operation Active-low assertion after accepting wakeup interrupt in standby mode until returning to normal operation with WDT overflow Note: H: high level; L: low level 8.1.3 Register Configuration Table 8.3 shows the control register configuration for the power-down modes. Table 8.3 Name Standby control register Standby control register 2 Register Configuration Abbreviation STBCR STBCR2 R/W R/W R/W Initial Value Access Size H'00* H'00* H'FFFFFF82 H'FFFFFF88 Address 8 8 Note: * Initialized by a power-on reset. This value is not initialized by a manual reset; the current value is retained. 8.2 8.2.1 Register Descriptions Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that sets the powerdown mode. STBCR is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7 STBY 0 R/W 6 -- 0 R 5 -- 0 R 4 STBXTL 0 R/W 3 -- 0 R 2 MSTP2 0 R/W 1 MSTP1 0 R/W 0 MSTP0 0 R/W Rev. 5.00, 09/03, page 183 of 760 Bit 7--Standby (STBY): Specifies transition to standby mode. Bit 7: STBY 0 1 Description Executing SLEEP instruction puts chip into sleep mode Executing SLEEP instruction puts chip into standby mode (Initial value) Bits 6, 5, and 3--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--Standby Crystal (STBXTL): Specifies halting or operating of the clock pulse generator in standby mode. Bit 4: STBXTL 0 1 Description Clock pulse generator is halted in standby mode Clock pulse generator is operates in standby mode (Initial value) Bit 2--Module Standby 2 (MSTP2): Specifies halting of the clock supply to the timer unit TMU (an on-chip peripheral module). When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted. Bit 2: MSTP2 0 1 Description TMU runs Clock supply to TMU is halted (Initial value) Bit 1--Module Standby 1 (MSTP1): Specifies halting of the clock supply to the realtime clock RTC (an on-chip peripheral module). When the MSTP1 bit is set to 1, the supply of the clock to the RTC is halted. When the clock halts, all RTC registers become inaccessible, but the counter keeps running. Bit 1: MSTP1 0 1 Description RTC runs Clock supply to RTC is halted (Initial value) Before switching the RTC to module standby, access at least one among the registers RTC, SCI, and TMU. Rev. 5.00, 09/03, page 184 of 760 Bit 0--Module Standby 0 (MSTP0): Specifies halting of the clock supply to the serial communication interface SCI (an on-chip peripheral module). When the MSTP0 bit is set to 1, the supply of the clock to the SCI is halted. Bit 0: MSTP0 0 1 Description SCI operates Clock supply to SCI is halted (Initial value) 8.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a readable/writable 8-bit register that sets the powerdown mode. STBCR2 is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 MSTP7 0 R/W 3 MSTP6 0 R/W 2 MSTP5 0 R/W 1 MSTP4 0 R/W 0 MSTP3 0 R/W MDCHG MSTP8 Bit 7--Reserved: The write value set in the program should always be 1. Bit 6--Pin MD5 to MD0 Control (MDCHG): Specifies whether or not pins MD5 to MD0 are changed in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when returning from standby mode by means of a reset or interrupt. Bit 6: MDCHG 0 1 Description Pins MD5 to MD0 are not changed in standby mode Pins MD5 to MD0 are changed in standby mode (Initial value) Bit 5-- Module Stop 8 (MSTP8): Specifies halting of the clock supply to the user break controller UBC (an on-chip peripheral module). When the MSTP8 bit is set to 1, the supply of the clock to the UBC is halted. Bit 5: MSTP8 0 1 Description UBC runs Clock supply to UBC is halted (Initial value) Rev. 5.00, 09/03, page 185 of 760 Bit 4--Module Stop 7 (MSTP7): Specifies halting of the clock supply to the DMAC (an on-chip peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is halted. Bit 4: MSTP7 0 1 Description DMAC runs Clock supply to DMAC halted (Initial value) Bit 3--Module Stop 6 (MSTP6): Specifies halting of the clock supply to the DAC (an on-chip peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted. Bit 3: MSTP6 0 1 Description DAC runs Clock supply to DAC halted (Initial value) Bit 2--Module Stop 5 (MSTP5): Specifies halting of the clock supply to the ADC (an on-chip peripheral module). When the MSTP5 bit is set to 1, the supply of the clock to the ADC is halted and all registers are initialized. Bit 2: MSTP5 0 1 Description ADC runs Clock supply to ADC halted and all registers initialized (Initial value) Bit 1--Module Stop 4 (MSTP4): Specifies halting of the clock supply to the SCI2 (SCIF) serial communication interface with FIFO (an on-chip peripheral module). When the MSTP1 bit is set to 1, the supply of the clock to SCI2 (SCIF) is halted. Bit 1: MSTP4 0 1 Description SCI2 (SCIF) runs Clock supply to SCI2 (SCIF) halted (Initial value) Bit 0--Module Stop 3 (MSTP3): Specifies halting of the clock supply to the SCI1 (IrDA) Infrared Data Association interface with FIFO (an on-chip peripheral module). When the MSTP3 bit is set to 1, the supply of the clock to SCI1 (IrDA) is halted. Bit 0: MSTP3 0 1 Description SCI1(IrDA) runs Clock supply to SCI1(IrDA) halted (Initial value) Rev. 5.00, 09/03, page 186 of 760 8.3 8.3.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO and CKIO2 pins. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low. 8.3.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip peripheral module, PINT) or reset. Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in the INTEVT and INTEVT2 registers. Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset. 8.3.3 Precautions when Using the Sleep Mode DMAC transfers should not be performed in the sleep mode under conditions other than when the clock ratio of I (on-chip clock) to B (bus clock) is 1:1. Rev. 5.00, 09/03, page 187 of 760 8.4 8.4.1 Standby Mode Transition to Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. In standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. The clock output from the CKIO and CKIO2 pins also halts. CPU and cache register contents are held, but some on-chip peripheral modules are initialized. Table 8.4 lists the states of registers in standby mode. Table 8.4 Module Interrupt controller (INTC) On-chip clock pulse generator (OSC) User break controller (UBC) Bus state controller (BSC) Timer unit (TMU) Realtime clock (RTC) A/D converter (ADC) D/A converter (DAC) Register States in Standby Mode Registers Initialized -- -- -- -- TSTR register -- All registers -- Registers Retaining Data All registers All registers All registers All registers Registers other than TSTR All registers -- All registers The procedure for moving to standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. Clear the WDT's timer counter (WTCNT) to 0 and the CKS2-CKS0 bits in the WTCSR register to appropriate values to secure the specified oscillation settling time. 2. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed. 3. Standby mode is entered and the clocks within the chip are halted. The STATUS1 pin output goes low and the STATUS0 pin output goes high. Rev. 5.00, 09/03, page 188 of 760 8.4.2 Canceling Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL, IRQ, PINT*1, or on-chip peripheral module (except interval timer)*2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low. Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT and INTEVT2 registers. After the branch to the interrupt handling routine, clear the STBY bit in the STBCR register. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues operation and a transition is made to standby mode*3 when it reaches H'80. This function prevents the data from being destroyed due to a rise in voltage with an unstable power supply, etc. Interrupts are accepted in standby mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an interrupt is detected, the phase of the CKIO pin clock output may be unstable, until the processor starts interrupt handling. (The canceling condition is that the IRL3-IRL0 level is higher than the mask level in the I3-I0 bits in the SR register.) Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3-IRL0, IRQ4- IRQ0, or PINT0/1. 2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC clock) interrupt. 3. This standby mode can be canceled only by a power-on reset. Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value H'FF WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR.STBY is cleared, WTCNT halts automatically. H'80 Time Figure 8.1 Canceling Standby Mode with STBCR.STBY Rev. 5.00, 09/03, page 189 of 760 Canceling with a Reset: Standby mode is canceled by a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO and CKIO2 pins. 8.4.3 Clock Pause Function In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter standby mode using the appropriate procedures. 2. Once standby mode is entered and the clock stopped within the chip, the STATUS1 pin output is low and the STATUS0 pin output is high. 3. Once the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped or the frequency is changed. 4. When the frequency is changed, an NMI, IRL, IRQ, PINT, or on-chip peripheral module (except interval timer) interrupt is input after the change. When the clock is stopped, the same interrupts are input after the clock is applied. 5. After the time set in the WDT has elapsed, the clock starts being applied internally within the chip, the STATUS1 and STATUS0 pins both go low, and operation resumes from interrupt exception handling. Rev. 5.00, 09/03, page 190 of 760 8.5 8.5.1 Module Standby Function Transition to Module Standby Function Setting the standby control register MSTP8-MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. The module standby function holds the state prior to halting the external pins of the on-chip peripheral modules. TMU external pins hold their state prior to the halt. SCI external pins go to the reset state. With a few exceptions, all registers hold their values. Bit MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description UBC runs Supply of clock to UBC halted DMAC runs Supply of clock to DMAC halted DAC runs Supply of clock to DAC halted ADC runs Supply of clock to ADC halted, and all registers initialized SCIF runs Supply of clock to SCIF halted IrDA runs Supply of clock to IrDA halted TMU runs Supply of clock to TMU halted. Registers initialized* RTC runs 23 Supply of clock to RTC halted. Register access prohibited* * 1 SCI runs Supply of clock to SCI halted Notes: 1. The registers initialized are the same as in standby mode (see table 8.4). 2. The counter runs. 3. Before switching the RTC to module standby, access at least one among the registers RTC, SCI, and TMU. 8.5.2 Clearing Module Standby Function The module standby function can be cleared by clearing the MSTPSLP0 and MSTP8-MSTP0 bits to 0, or by a power-on reset or manual reset. Rev. 5.00, 09/03, page 191 of 760 8.6 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 to 8.8. 8.6.1 Timing for Resets Power-On Reset CKIO, CKIO2*4 PLL settling time RESETP STATUS Normal*2 Reset*1 Normal*2 RESETOUT 0 to 5 Bcyc*3 Notes: 1. 2. 3. 4. 0 to 30 Bcyc*3 Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output Rev. 5.00, 09/03, page 192 of 760 Manual Reset CKIO, CKIO2*5 RESETM STATUS Normal*3 Reset*2 Normal*3 RESETOUT 0 Bcyc or more*4 Notes: 1. 2. 3. 4. 5. 0 to 30 Bcyc*4 In a manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.3 Manual Reset STATUS Output Rev. 5.00, 09/03, page 193 of 760 8.6.2 Timing for Canceling Standby Standby to Interrupt Oscillation stops Interrupt request WDT overflow CKIO, CKIO2*3 WDT count STATUS Normal*2 Standby*1 Normal*2 WAKEUP Notes: 1. 2. 3. Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.4 Standby to Interrupt STATUS Output Rev. 5.00, 09/03, page 194 of 760 Standby to Power-On Reset Oscillation stops Reset CKIO, CKIO2*7 RESETP*1 STATUS Normal*5 Standby*4 *2 Reset*3 0 to 30 Bcyc*6 Normal*5 0 to 10 Bcyc*6 Notes: 1. 2. 3. 4. 5. 6. 7. When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during the PLL's oscillation settling time. Undefined Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.5 Standby to Power-On Reset STATUS Output Rev. 5.00, 09/03, page 195 of 760 Standby to Manual Reset Oscillation stops Reset CKIO, CKIO2*6 RESETM*1 STATUS Normal*4 Standby*3 Reset*2 0 to 20 Bcyc*5 Normal*4 Notes: 1. 2. 3. 4. 5. 6. When standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL's oscillation settling time. Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.6 Standby to Manual Reset STATUS Output 8.6.3 Timing for Canceling Sleep Mode Sleep to Interrupt Interrupt request CKIO, CKIO2*3 STATUS Normal*2 Sleep*1 Normal*2 Notes: 1. 2. 3. Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.7 Sleep to Interrupt STATUS Output Rev. 5.00, 09/03, page 196 of 760 Sleep to Power-On Reset Reset CKIO, CKIO2*7 RESETP*1 STATUS Normal*5 Sleep*4 *2 Reset*3 0 to 30 Bcyc*6 Normal*5 0 to 10 Bcyc*6 Notes: 1. 2. 3. 4. 5. 6. 7. When the PLL1's multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL's oscillation settling time. Undefined Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.8 Sleep to Power-On Reset STATUS Output Rev. 5.00, 09/03, page 197 of 760 Sleep to Manual Reset Reset CKIO, CKIO2*6 RESETM*1 STATUS Normal*4 Sleep*3 0 to 80 Bcyc*5 Reset*2 0 to 30 Bcyc*5 Normal*4 Notes: 1. 2. 3. 4. 5. 6. Keep RESETM low until STATUS becomes reset. Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.9 Sleep to Manual Reset STATUS Output Rev. 5.00, 09/03, page 198 of 760 8.7 8.7.1 Hardware Standby Mode Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the standby mode entered on execution of a SLEEP instruction ((software) standby mode). Hardware standby mode differs from (software) standby mode as follows. 1. Interrupts and manual resets are not accepted. 2. The TMU does not operate. Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows. 1. In standby mode The clock remains stopped and the chip enters the hardware standby state. Acceptance of interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts. 2. During WDT operation when standby mode is canceled by an interrupt The chip enters hardware standby mode after standby mode is canceled and the CPU resumes operation. 3. In sleep mode The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes operation. Hold the CA pin low in hardware standby mode. 8.7.2 Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the CPU begins power-on reset processing. Operation is not guaranteed in the event of an interrupt or manual reset. Rev. 5.00, 09/03, page 199 of 760 8.7.3 Hardware Standby Mode Timing Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode. Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low. Rcyc: EXTAL2 (32.768 kHz) cycle CKIO, CKIO2*6 CA RESETP STATUS Normal*3 2 Rcyc or more*5 Standby*2 Undefined Reset*1 0-10Bcyc*4 Notes: 1. 2. 3. 4. 5. 6. Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.10 Hardware Standby Mode (When CA Goes Low in Normal Operation) Rev. 5.00, 09/03, page 200 of 760 CKIO, CKIO2*6 CA RESETP STATUS Standby Normal*3 Standby*2 Undefined Reset*1 WDT operation 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. 6. 0-10 Bcyc*4 Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) cycle The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) Rev. 5.00, 09/03, page 201 of 760 Rev. 5.00, 09/03, page 202 of 760 Section 9 On-Chip Oscillation Circuits 9.1 Overview The on-chip oscillation circuits consist of a clock pulse generator (CPG) block and a watchdog timer (WDT) block. The WDT is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. 9.1.1 Features The CPG has the following features: * Four clock modes: Selection of four clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. * Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I); a peripheral clock (P) for the on-chip peripheral modules; and a bus clock (CKIO) for the external bus interface. * Frequency change function: Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control: The clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. The WDT has the following features: * Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Selection of power-on reset or manual reset. * Generates interrupts in interval timer mode: Internal timer interrupts occur after counter overflow. * Selection of eight counter input clocks. Eight clocks (x1 to x1/4096) can be obtained by dividing the peripheral clock. Rev. 5.00, 09/03, page 203 of 760 9.2 9.2.1 Overview of CPG CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1. Clock pulse generator CAP1 PLL circuit 1 (x 1, 2, 3, 4, 6) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 Divider 1 x1 x 1/2 x 1/3 x 1/4 x 1/6 Internal clock (I) Cycle = Icyc Peripheral clock (P) Cycle = Pcyc CPG control unit Clock frequency control circuit Standby control circuit Standby control MD2 MD1 MD0 FRQCR STBCR Bus interface Internal bus Legend FRQCR: Frequency control register STBCR: Standby control register Figure 9.1 Block Diagram of Clock Pulse Generator Rev. 5.00, 09/03, page 204 of 760 The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin. 2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal oscillator or the input clock frequency from the EXTAL pin. The multiplication ratio is fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 9.3 for more information on clock operation modes. 3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL pins. It operates according to the clock operating mode setting. 4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock. The operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of PLL circuit 1, as long as it is not lower than the CKIO pin clock frequency. The division ratio is set in the frequency control register. 5. Divider 2: Divider 2 generates a clock at the operating frequency used by the peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of PLL circuit 1 or the CKIO pin clock frequency, as long as it is not higher than the CKIO pin clock frequency. The division ratio is set in the frequency control register. 6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD pins and the frequency control register. 7. Standby Control Circuit: The standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. Frequency Control Register: The frequency control register has control bits assigned for the following functions: the frequency multiplication ratio of PLL 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. Standby Control Register: The standby control register has bits for controlling the power-down modes. See section 8, Power-Down Modes, for more information. Rev. 5.00, 09/03, page 205 of 760 9.2.2 CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 Pin Name Mode control pins CPG Pins and Functions Symbol MD0 MD1 MD2 XTAL EXTAL CKIO CAP1 CAP2 I/O I I I O I I/O I I Connects a crystal oscillator Connects a crystal oscillator. Also used to input an external clock Inputs or outputs an external clock Connects capacitor for PLL circuit 1 operation (recommended value 470 pF) Connects capacitor for PLL circuit 2 operation (recommended value 470 pF) Description Set the clock operating mode Crystal I/O pins (clock input pins) Clock I/O pin Capacitor connection pins for PLL 9.2.3 CPG Register Configuration Table 9.2 shows the CPG register configuration. Table 9.2 CPG Register Abbreviation FRQCR R/W R/W Initial Value H'0102 Address H'FFFFFF80 Access Size 16 Register Name Frequency control register Rev. 5.00, 09/03, page 206 of 760 9.3 Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2-MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes Pin Values Mode 0 MD2 MD1 MD0 0 0 0 Clock I/O Source Output EXTAL CKIO PLL2 PLL1 Divider 1 Divider 2 CKIO On/Off On/Off Input Input Frequency On, On multiplication ratio: 1 On, On multiplication ratio: 4 On, On multiplication ratio: 4 Off On PLL1 output PLL1 (EXTAL) 1 0 0 1 EXTAL CKIO PLL1 output PLL1 (EXTAL) x 4 2 0 1 0 Crystal CKIO oscillator PLL1 output PLL1 (Crystal) x 4 7 -- 1 1 1 CKIO -- PLL1 output PLL1 (CKIO) Except above value Reserved Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside the chip. PLL circuit 1 is constantly on. An input clock frequency of 25 MHz to 66.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside the chip, allowing a low-frequency external clock to be used. An input clock frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside the chip, allowing a low crystal frequency to be used. A crystal oscillation frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Rev. 5.00, 09/03, page 207 of 760 Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to the chip. In modes 0 to 2, the system clock is generated from the output of the chip's CKIO pin. Consequently, if a large number of ICs are operating on the clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by distributing the clocks to each one. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Table 9.4 Available Combinations of Clock Mode and FRQCR Values PLL2 Clock Rate* Input Frequency (I:B:P) Range 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz CKIO Frequency Range 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz Clock Mode FRQCR PLL1 0 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 ON (x 1) ON (x 1) 1:1:1 ON (x 1) ON (x 1) 1:1:1/2 ON (x 1) ON (x 1) 1:1:1/4 ON (x 2) ON (x 1) 2:1:1 ON (x 2) ON (x 1) 2:1:1/2 ON (x 2) ON (x 1) 1:1:1 ON (x 2) ON (x 1) 1:1:1/2 ON (x 4) ON (x 1) 4:1:1 ON (x 4) ON (x 1) 2:1:1 ON (x 4) ON (x 1) 1:1:1 ON (x 3) ON (x 1) 3:1:1 ON (x 3) ON (x 1) 3:1:1/2 ON (x 3) ON (x 1) 1:1:1 ON (x 3) ON (x 1) 1:1:1/2 ON (x 6) ON (x 1) 6:1:1 Rev. 5.00, 09/03, page 208 of 760 Clock Mode FRQCR PLL1 1, 2 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 7 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 PLL2 Clock Rate* Input Frequency (I:B:P) Range 6.25 MHz to 8.34 MHz CKIO Frequency Range 25 MHz to 33.34 MHz ON (x 1) ON (x 4) 4:4:4 ON (x 1) ON (x 4) 4:4:2 ON (x 1) ON (x 4) 4:4:1 ON (x 2) ON (x 4) 8:4:4 ON (x 2) ON (x 4) 8:4:2 ON (x 2) ON (x 4) 4:4:4 ON (x 2) ON (x 4) 4:4:2 ON (x 4) ON (x 4) 16:4:4 ON (x 4) ON (x 4) 8:4:4 ON (x 4) ON (x 4) 4:4:4 ON (x 3) ON (x 4) 12:4:4 ON (x 3) ON (x 4) 12:4:2 ON (x 3) ON (x 4) 4:4:4 ON (x 3) ON (x 4) 4:4:2 ON (x 6) ON (x 4) 24:4:4 ON (x 1) OFF ON (x 1) OFF ON (x 1) OFF ON (x 2) OFF ON (x 2) OFF ON (x 2) OFF ON (x 2) OFF ON (x 4) OFF ON (x 4) OFF ON (x 4) OFF ON (x 3) OFF ON (x 3) OFF ON (x 3) OFF ON (x 3) OFF ON (x 6) OFF 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 3:1:1/2 1:1:1 1:1:1/2 6:1:1 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz Do not set values other than those in the table above in the FRQCR register. Note: * Taking input clock as 1. Rev. 5.00, 09/03, page 209 of 760 Cautions: 1. The frequency of the internal clock (I) becomes: * * * * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. Do not set the internal clock frequency lower than the CKIO pin frequency. The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. The peripheral clock frequency should not be set higher than the frequency of the CKIO pin, higher than 33.34 MHz. 2. The frequency of the peripheral clock (P) becomes: 3. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. 4. x 1, x 2, x 3, x 4, or x 6 can be used as the multiplication ratio of PLL circuit 1. x 1, x 1/2, x 1/3, x 1/4, and x 1/6 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 is determined by the mode. Rev. 5.00, 09/03, page 210 of 760 9.4 9.4.1 Register Descriptions Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify the frequency multiplication ratio of PLL circuit 1 and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. FRQCR: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 STC2 0 R/W 7 -- 0 R 14 IFC2 0 R/W 6 -- 0 R 13 PFC2 0 R/W 5 STC1 0 R/W 12 -- 0 R 4 STC0 0 R/W 11 -- 0 R 3 IFC1 0 R/W 10 -- 0 R 2 IFC0 0 R/W 9 -- 0 R 1 PFC1 1 R/W 8 -- 1 R 0 PFC0 0 R/W Bits 15, 5, and 4--Frequency Multiplication Ratio (STC): These bits specify the frequency multiplication ratio of PLL circuit 1. Bit 15: STC2 0 0 1 0 1 Bit 5: STC1 0 0 0 1 0 Bit 4: STC0 0 1 0 0 1 Description x1 x2 x3 x4 x6 Reserved (Initial value) Except above value Rev. 5.00, 09/03, page 211 of 760 Bits 14, 3, and 2--Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 0 0 1 0 Bit 3: IFC1 0 0 0 1 Bit 2: IFC0 0 1 0 0 Description x1 x 1/2 x 1/3 x 1/4 Reserved (Setting prohibited) (Initial value) Except above value Note: Do not set the internal clock frequency lower than the CKIO pin frequency. Bits 13, 1, and 0--Peripheral Clock Frequency Division Ratio (PFC): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin. Bit 13: PFC2 0 0 1 0 1 Bit 1: PFC1 0 0 0 1 0 Bit 0: PFC0 0 1 0 0 1 Description x1 x 1/2 x 1/3 x 1/4 x 1/6 Reserved (Setting prohibited) (Initial value) Except above value Note: Do not set the peripheral clock frequency higher than the CKIO pin frequency. Bits 12 to 9, 7, and 6--Reserved: These bits are always read as 0. The write value should always be 0. Bit 8--Reserved: This bit is always read as 1. The write value should always be 1. Rev. 5.00, 09/03, page 212 of 760 9.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication ratio of PLL circuit 1 or by changing the division ratios of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below. To the FRQCR register, do not set values other than those given in table 9.4. 9.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2-CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC2 to STC0 bits. The division ratio can also be set in the IFC2- IFC0 bits and PFC2-PFC0 bits. 4. The processor pauses internally and the WDT starts incrementing. In clock modes 0-2 and 7, the internal and peripheral clocks both stop. (except for the peripheral clock supplied to the WDT) 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. * * * Bits IFC2 to IFC0 are changed. STC2 to STC0 are not changed. The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. Changing the Division Ratio 9.5.2 The WDT will not count unless the multiplication ratio is changed simultaneously. 1. In the initial state, IFC2-IFC0 = 000 and PFC2-PFC0 = 010. 2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication ratio of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio. Rev. 5.00, 09/03, page 213 of 760 9.6 9.6.1 Overview of WDT Block Diagram of WDT Figure 9.2 shows a block diagram of the WDT. WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Divider Clock selection Clock selector Interrupt control WTCSR Bus interface Overflow Clock WTCNT Reset control Legend WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 9.2 Block Diagram of WDT 9.6.2 Register Configuration The WDT has two registers that select the clock, switch the timer mode, and perform other functions. Table 9.5 shows the WDT registers. Table 9.5 Name Watchdog timer counter Watchdog timer control/status register Register Configuration Abbreviation WTCNT WTCSR R/W Initial Value Address H'FFFFFF84 H'FFFFFF86 Access Size R: 8; W: 16* R: 8; W: 16* R/W * H'00 R/W * H'00 Note: * Write with word access. Write with H'5A and H'A5, respectively, in the upper byte. Byte or longword writes are not possible. Read with byte access. Rev. 5.00, 09/03, page 214 of 760 9.7 9.7.1 WDT Registers Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the selected clock. WTCNT differs from other registers in that it is more difficult to write to. See section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to H'00 only by a power-on reset through the RESETP pin. Use word access to write to the WTCNT counter, with H'5A in the upper byte. Use byte access to read WTCNT. Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 9.7.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR differs from other registers in that it is more difficult to write to. See section 9.7.3, Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow causes an internal reset, WTCSR retains its value. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use word access to write to the WTCSR counter, with H'A5 in the upper byte. Use byte access to read WTCSR. Bit: Initial value: R/W: 7 TME 0 R/W 6 WT/IT 0 R/W 5 RSTS 0 R/W 4 WOVF 0 R/W 3 IOVF 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. Bit 7: TME 0 1 Description Timer disabled: Count-up stops and WTCNT value is retained (Initial value) Timer enabled Rev. 5.00, 09/03, page 215 of 760 Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an I interval timer. Bit 6: WT/IT I 0 1 Description Used as interval timer Used as watchdog timer (Initial value) Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. Bit 5--Reset Select (RSTS): Selects the type of reset when WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) Note: RESETOUT is output. Bit 4--Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. Bit 4: WOVF 0 1 Description No overflow WTCNT has overflowed in watchdog timer mode (Initial value) Bit 3--Interval Timer Overflow (IOVF): Indicates that WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. Bit 3: IOVF 0 1 Description No overflow WTCNT has overflowed in interval timer mode (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period in the table is the value when the peripheral clock (P) is 15 MHz. Rev. 5.00, 09/03, page 216 of 760 Bit 2: CKS2 0 Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 0 1 0 1 Clock Division Ratio 1 1/4 1/16 1/32 1/64 1/256 1/1024 1/4096 (Initial value) Overflow Period (when P = 15 MHz) 17 s 68 s 273 s 546 s 1.09 ms 4.36 ms 17.48 ms 69.91 ms 1 0 1 Note: If bits CKS2-CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. 9.7.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to using a word transfer instruction. They cannot be written to with a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 9.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 Address: H'FFFFFF84 H'5A 8 7 Write data 0 WTCSR write 15 Address: H'FFFFFF86 H'A5 8 7 Write data 0 Figure 9.3 Writing to WTCNT and WTCSR Rev. 5.00, 09/03, page 217 of 760 9.8 9.8.1 Using the WDT Canceling Standby The WDT can be used to cancel standby mode with an NMI or other interrupt. The procedure is described below. (The WDT does not run when a reset is used for canceling, so keep the RESET pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2-CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Switch to standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal or detecting interrupts. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt handling routine and this will stop the WDT. When the STBY bit remains at 1, the SH7709S again enters standby mode when the WDT has counted up to H'80. This standby mode can be canceled by a power-on reset. 9.8.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2-CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written to, the clock stops and the processor enters standby mode temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 5. The counter stops at a value of H'00 or H'01. The stop value depends on the clock ratio. Rev. 5.00, 09/03, page 218 of 760 When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. * * * Bits IFC2 to IFC0 are changed. STC2 to STC0 are not changed. The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. Using Watchdog Timer Mode 9.8.3 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2-CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. When a reset is generated, a low level is output at the RESETOUT pin, and a high level at the STATUS0 and STATUS1 pins. The output period is approximately 1 count clock cycle in the case of a poweron reset, and approximately 5 peripheral clock cycles in the case of a manual reset. 9.8.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2- CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. Rev. 5.00, 09/03, page 219 of 760 9.9 Notes on Board Design When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2 close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. Avoid crossing signal lines CL1 CL2 EXTAL XTAL SH7709S Note: The values for CL1 and CL2 should be determined after consultation with the crystal manufacturer. Figure 9.4 Points for Attention when Using Crystal Resonator Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.1 to 1 F as a passive capacitor for each VSS/VCC pair. Mount the passive capacitors close to the SH7709S power supply pins, and use components with a frequency characteristic suitable for the chip's operating frequency, as well as a suitable capacitance value. Digital system VSS/VCC pairs: 19-21, 27-29, 33-35, 45-47, 57-59, 69-71, 79-81, 83-85, 95-97, 109111, 132-134, 153-154, 161-163, 173-175, 181-183, 205-208 On-chip oscillator VSS/VCC pairs: 3-6, 145-147, 148-150 Note: The pin numbers above apply to LQFP and HQFP packages. When Using a PLL Oscillator Circuit: Keep the wiring from the PLL V CC and VSS connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. Ground the oscillation stabilization capacitors C1 and C2 to V SS (PLL1) and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to V CC or VSS and leave the XTAL pin open. Rev. 5.00, 09/03, page 220 of 760 Avoid crossing signal lines VCC (PLL2) Power supply CAP2 VSS (PLL2) VCC (PLL1) VSS CAP1 C1 VSS (PLL1) C2 VCC Reference values C1 = 470 pF C2 = 470 pF Figure 9.5 Points for Attention when Using PLL Oscillator Circuit Rev. 5.00, 09/03, page 221 of 760 Rev. 5.00, 09/03, page 222 of 760 Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable the chip to link directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 10.1.1 Features The BSC has the following features: * Physical address space is divided into six areas A maximum 64 Mbytes for each of the six areas, 0, 2-6 Area bus width can be selected by register (area 0 is set by external pin) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled through software. Register settings can be used to specify the insertion of 1-10 cycles independently for each area (1-38 cycles for areas 5 and 6 and the PCMCIA interface only) The type of memory connected can be specified for each area, and control signals are output for direct memory connection Wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads in the same area * Direct interface to synchronous DRAM Multiplexes row/column addresses according to synchronous DRAM capacity Supports burst operation Supports bank active mode Has both auto-refresh and self-refresh functions Controls timing of synchronous DRAM direct-connection control signals according to register setting * Burst ROM interface Insertion of wait states controllable through software Register setting control of burst transfers * PCMCIA direct-connection interface Insertion of wait states controllable through software Bus sizing function for I/O bus width (only in little-endian mode) Rev. 5.00, 09/03, page 223 of 760 * Short refresh cycle control The overflow interrupt function of the refresh counter enables the refresh function immediately after a self-refresh operation using low power-consumption DRAM * The refresh counter can be used as an interval timer Outputs an interrupt request signal using the compare-match function Outputs an interrupt request signal when the refresh counter overflows Rev. 5.00, 09/03, page 224 of 760 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the bus state controller. Bus interface WAIT Wait controller WCR1 WCR2 CS0, CS6 to CS2, CE2A, CE2B MCS0 to MCS7 BS RD RD/WR WE3 to WE0 RASxx CASx CKE ICIORD, ICIOWR IOIS16 Area controller BCR1 BCR2 MCR Memory controller PCR MCSCRn Peripheral bus RFCR RTCNT Refresh controller Comparator RTCOR RTCSR BSC Interrupt controller Legend WCR: Wait state control register BCR: Bus control register MCR: Memory control register PCR: PCMCIA control register RFCR: RTCNT: RTCOR: RTCSR: MCSCRn: Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register MCSn control register (n = 0-7) Figure 10.1 Block Diagram of Bus State Controller Rev. 5.00, 09/03, page 225 of 760 Module bus Internal bus 10.1.3 Pin Configuration Table 10.1 shows the BSC pin configuration. Table 10.1 BSC Pins Pin Name Address bus Data bus Bus cycle start Chip select 0, 2-4 Chip select 5, 6 Signal A25-A0 D15-D0 D31-D16 BS CS0, CS2-CS4 CS5/CE1A, CS6/CE1B CE2A, CE2B RD/WR RAS3L RAS3U CASL CASU WE0/DQMLL I/O O I/O I/O O O O Description Address output Data I/O Data I/O when using 32-bit bus width Shows start of bus cycle. During burst transfers, asserted every data cycle. Chip select signals to indicate area being accessed. Chip select signals to indicate area being accessed. CS5/CE1A and CS6/CE1B can also be used as CE1A and CE1B of PCMCIA. CE2A and CE2B signals when PCMCIA is used Data bus direction indication signal. PCMCIA write indication signal. When synchronous DRAM is used, RAS3L for lower 32-Mbyte address and 64-Mbyte address. When synchronous DRAM is used, RAS3U for upper 32-Mbyte address. When synchronous DRAM is used, CASL signal for lower 32-Mbyte address and 64-Mbyte address. When synchronous DRAM is used, CASU signal for upper 32-Mbyte address. When memory other than synchronous DRAM is used, D7-D0 write strobe signal. When synchronous DRAM is used, selects D7-D0. When memory other than synchronous DRAM and PCMCIA is used, D15-D8 write strobe signal. When synchronous DRAM is used, selects D15-D8. When PCMCIA is used, strobe signal indicating write cycle. When memory other than synchronous DRAM and PCMCIA is used, D23-D16 write strobe signal. When synchronous DRAM is used, selects D23- D16. When PCMCIA is used, strobe signal indicating I/O read. PCMCIA card select Read/write Row address strobe 3L Row address strobe 3U Column address strobe Column address strobe LH Data enable 0 O O O O O O O Data enable 1 WE1/DQMLU/ WE O Data enable 2 WE2/DQMUL/ ICIORD O Rev. 5.00, 09/03, page 226 of 760 Pin Name Data enable 3 Signal WE3/DQMUU/ ICIOWR I/O O Description When memory other than synchronous DRAM and PCMCIA is used, D31-D24 write strobe signal. When synchronous DRAM is used, selects D31- D24. When PCMCIA is used, strobe signal indicating I/O write. Strobe signal indicating read cycle Wait state request signal Clock enable control signal for synchronous DRAM Signal indicating PCMCIA 16-bit I/O. Valid only in little-endian mode. Bus release request signal Bus release acknowledge signal Chip select signal for mask ROM connected to area 0 or 2. Read Wait Clock enable IOIS16 Bus release request Bus release acknowledgment Mask ROM chip select RD WAIT CKE IOIS16 BREQ BACK O I O I I O MCS[0]- MCS[7] O Rev. 5.00, 09/03, page 227 of 760 10.1.4 Register Configuration The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, and refreshes devices. Table 10.2 BSC Registers Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 Individual memory control register PCMCIA control register Refresh timer control/status register Refresh timer counter Refresh time constant register Refresh count register Synchronous DRAM mode register, area 2 Synchronous DRAM mode register, area 3 MCS0 control register MCS1 control register MCS2 control register MCS3 control register MCS4 control register MCS5 control register MCS6 control register MCS7 control register MCSCR0 MCSCR1 MCSCR2 MCSCR3 MCSCR4 MCSCR5 MCSCR6 MCSCR7 R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Abbr. BCR1 BCR2 WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Initial Value* Address H'0000 H'3FF0 H'3FF3 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 -- H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 Bus Width 16 16 16 16 16 16 16 16 16 16 H'FFFFD000- 8 H'FFFFDFFF H'FFFFE000- H'FFFFEFFF H'FFFFFF50 H'FFFFFF52 H'FFFFFF54 H'FFFFFF56 H'FFFFFF58 H'FFFFFF5A H'FFFFFF5C H'FFFFFF5E 16 16 16 16 16 16 16 16 Notes: For details, see section 10.2.7, Synchronous DRAM Mode Register (SDMR). * Initialized by a power-on reset. Rev. 5.00, 09/03, page 228 of 760 10.1.5 Area Overview Space Allocation: In the architecture of the SH7709S, both logical spaces and physical spaces have 32-bit address spaces. The logical space is divided into five areas by the value of the upper bits of the address. The physical space is divided into eight areas. Logical space can be allocated to physical space using a memory management unit (MMU). For details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for physical space. As shown in table 10.3, the SH7709S can be connected directly to six memory/PCMCIA interface areas, and it outputs chip select signals (CS0, CS2-CS6, CE2A, CE2B) for each of them. CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the corresponding bytes accessed. H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 P0, U0 Area 0 (CS0) Internal I/O Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5 (CS5) Area 6 (CS6) Reserved area H'00000000 H'04000000 H'08000000 H'0C000000 H'10000000 H'14000000 H'18000000 Physical address space Logical address space Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can optionally generate a physical address for the logical address. This diagram can be applied when the MMU is off, and when the MMU is on and each physical address corresponding to a logical address is equal except for the upper three bits. When translating logical addresses to arbitrary physical addresses, refer to table 10.3. Figure 10.2 Correspondence between Logical Address Space and Physical Address Space Rev. 5.00, 09/03, page 229 of 760 Table 10.3 Physical Address Space Map Area 0 Connectable Memory 1 Ordinary memory* , burst ROM Physical Address H'00000000 to H'03FFFFFF H'00000000 + H'20000000 x n to H'03FFFFFF + H'20000000 x n Capacity 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow 32 Mbytes 32 Mbytes Shadow 32 Mbytes Shadow Access Size 2 8, 16, 32* n = 1-6 8, 16, 32* n = 1-6 34 8, 16, 32* * 3 1 Internal I/O registers* 7 H'04000000 to H'07FFFFFF H'04000000 + H'20000000 x n to H'07FFFFFF + H'20000000 x n 2 Ordinary memory* , synchronous DRAM Ordinary memory* , synchronous DRAM Ordinary memory* 1 1 1 H'08000000 to H'0BFFFFFF H'08000000 + H'20000000 x n to H'0BFFFFFF + H'20000000 x n H'0C000000 to H'0FFFFFFF H'0C000000 + H'20000000 x n to H'0FFFFFFF + H'20000000 x n H'10000000 to H'13FFFFFF H'10000000 + H'20000000 x n to H'13FFFFFF + H'20000000 x n n = 1-6 34 8, 16, 32* * 3 n = 1-6 8, 16, 32* n = 1-6 35 8, 16, 32 * * 3 4 5 1 Ordinary memory* , PCMCIA, burst ROM H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF H'18000000 + H'20000000 x n to H'1BFFFFFF + H'20000000 x n Ordinary memory, burst ROM 6 1 Ordinary memory* , PCMCIA, burst ROM n = 1-6 35 8, 16, 32 * * n = 1-6 n = 0-7 7* 6 Reserved area H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n Notes: 1. 2. 3. 4. 5. 6. Memory with interface such as SRAM or ROM. Use external pin to specify memory bus width. Use register to specify memory bus width. With synchronous DRAM interfaces, bus width must be 16 or 32 bits. With PCMCIA interface, bus width must be 8 or 16 bits. Do not access the reserved area. If the reserved area is accessed, correct operation cannot be guaranteed. 7. When the control register in area 1 is not used for address translation by the MMU, set the first three bits of the logical address to 101 for allocation to the P2 space. Rev. 5.00, 09/03, page 230 of 760 Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 Area 3: H'0C000000 Area 4: H'10000000 Ordinary memory/ burst ROM Internal I/O Ordinary memory/ synchronous DRAM Ordinary memory/ synchronous DRAM Ordinary memory Area 5: H'14000000 Area 6: H'18000000 Ordinary memory/ burst ROM/PCMCIA Ordinary memory/ burst ROM/PCMCIA The PCMCIA interface is shared by the memory and I/O card The PCMCIA interface is shared by the memory and I/O card Figure 10.3 Physical Space Allocation Memory Bus Width: The memory bus width in the SH7709S can be set for each area. In area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the external pins (MD4 and MD3) and the memory size is shown in table below. Table 10.4 Correspondence between External Pins (MD4 and MD3) and Memory Size MD4 0 0 1 1 MD3 0 1 0 1 Memory Size Reserved (Do not set) 8 bits 16 bits 32 bits For areas 2-6, byte, word, and longword can be chosen for the bus width using bus control register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used. When the synchronous DRAM interface is used, word or longword can be chosen as the bus width. When the PCMCIA interface is used, set the bus width to byte or word. When synchronous DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When using the port function, set each of the bus widths to byte or word for all areas. For more information, see section 10.2.2, Bus Control Register 2 (BCR2). Rev. 5.00, 09/03, page 231 of 760 Shadow Space: Areas 0 and 2-6 are decoded by physical addresses A28-A26, which correspond to areas 000 to 110. Address bits 31-29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 x n (n = 1-6). The address range for area 7, which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 x n-H'1FFFFFFF + H'20000000 x n (n = 0-7) corresponding to the area 7 shadow space is reserved, and must not be used. 10.1.6 PCMCIA Support The SH7709S supports PCMCIA standard interface specifications in physical space areas 5 and 6. The interfaces supported are basically the "IC memory card interface" and "I/O card interface" stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1). Table 10.5 PCMCIA Interface Characteristics Item Access Data bus Memory type Memory capacity I/O space capacity Other features Feature Random access 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Maximum 32 Mbytes Maximum 32 Mbytes Dynamic bus sizing of I/O bus width * The PCMCIA interface can be accessed from the address translation area or non-address translation area. Note: * Dynamic bus sizing of the I/O bus width is supported only in little-endian mode. Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 Common memory/Attribute memory I/O space Common memory/Attribute memory I/O space Figure 10.4 PCMCIA Space Allocation Rev. 5.00, 09/03, page 232 of 760 Table 10.6 PCMCIA Support Interface IC Memory Card Interface Pin Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 I I I I I I I I I I I I/O Function -- Ground Signal GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM IREQ VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 I I I I I I I I I I I I/O Card Interface I/O Function -- Ground SH7709S Pin -- D3 D4 D5 D6 D7 CE1A or CE1B A10 RD A11 A9 A8 A13 A14 WE -- -- -- A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Ready/Busy Operation power Program power Address Address Address Address Address Address Address Address Address Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Ready/Busy Operation power Program/ peripheral power Address Address Address Address Address Address Address Address Address Address Address I/O Data I/O Data Rev. 5.00, 09/03, page 233 of 760 IC Memory Card Interface Pin Signal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 D1 D2 WP GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2 RESET WAIT RFU I I I I I I O I I I I I O I/O Function I/O Data I/O Data O Write protect Ground Ground Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I Card enable Voltage sense 1 Reserved Reserved Address Address Address Address Address Power supply Program power Address Address Address Address Voltage sense 2 Reset Wait request Reserved Signal D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2 RESET WAIT INPACK I/O Card Interface I/O Function I/O Data I/O Data O 16-bit I/O port Ground Ground O Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I Card enable Voltage sense 1 I/O read I/O write Address Address Address Address Address Power supply Program/ peripheral power I I I I I I O O Address Address Address Address Voltage sense 2 Reset Wait request SH7709S Pin D1 D2 IOIS16 -- -- -- D11 D12 D13 D14 D15 CE2A or CE2B -- ICIORD ICIOWR A17 A18 A19 A20 A21 -- -- A22 A23 A24 A25 -- -- -- Input acknowledge -- Rev. 5.00, 09/03, page 234 of 760 IC Memory Card Interface Pin Signal 61 62 63 64 65 66 67 68 REG BVD2 BVD1 D8 D9 D10 CD2 GND I/O Function I O O Attribute memory space select Battery voltage detection Battery voltage detection Signal REG SPKR STSCHG D8 D9 D10 CD2 GND I/O Card Interface I/O Function I O O Attribute memory space select SH7709S Pin -- Digital voice signal -- Card state change -- D8 D9 D10 -- -- I/O Data I/O Data I/O Data O Card detection Ground I/O Data I/O Data I/O Data O Card detection Ground 10.2 10.2.1 BSC Registers Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 16-bit readable/writable register that sets the functions and bus cycle state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Do not access external memory outside area 0 until BCR1 register initialization is complete. Bit: Initial value: R/W: Bit: 15 PULA 0 R/W 7 14 PULD 0 R/W 6 13 0 R/W 5 12 0 R/W 4 DRAM TP2 0 R/W 11 0/1* R 3 DRAM TP1 0 R/W 10 0 R/W 2 DRAM TP0 0 R/W 9 0 R/W 1 8 0 R/W 0 HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 A5BST0 A6BST1 A6BST0 Initial value: R/W: 0 R/W 0 R/W 0 R/W A5 PCM A6 PCM 0 R/W 0 R/W Note: * Samples the value of the external pin (MD5) designating the endian in a power-on reset. Rev. 5.00, 09/03, page 235 of 760 Bit 15--Pin A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up for 4 cycles immediately after BACK is asserted. Bit 15: PULA 0 1 Description Not pulled up Pulled up (Initial value) Bit 14--Pin D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up when not in use. Bit 14: PULD 0 1 Description Not pulled up Pulled up (Initial value) Bit 13--Hi-Z Memory Control (HIZMEM): Specifies the state of A25-A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 in standby mode. Bit 13: HIZMEM 0 1 Description A25-A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 are Hi-Z in standby mode (Initial value) A25-A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 are high in standby mode Bit 12--High-Z Control (HIZCNT): Specifies the state of the RAS and CAS signals in standby mode and when the bus is released. Bit 12: HIZCNT 0 1 Description RAS and CAS signals are high-impedance (High-Z) in standby mode and when bus is released (Initial value) RAS and CAS signals are driven in standby mode and when bus is released Bit 11--Endian Flag (ENDIAN): Samples the value of the external pin designating the endian in a power-on reset. The endian for all physical spaces is decided by this bit, which is read-only. Bit 11: ENDIAN 0 1 Description (On reset) Endian setting external pin (MD5) is low. Indicates the SH7709S is set as big-endian (On reset) Endian setting external pin (MD5) is high. Indicates the SH7709S is set as little-endian Rev. 5.00, 09/03, page 236 of 760 Bits 10 and 9--Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst ROM in physical space area 0. When burst ROM is used, these bits set the number of burst transfers. Bit 10: A0BST1 0 Bit 9: A0BST0 0 1 1 0 Description Access area 0 accessed as ordinary memory (Initial value) Access area 0 accessed as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Access area 0 accessed as burst ROM (8 consecutive accesses). Can be used when bus width is 8 or 16. Should not be specified when bus width is 16 or 32. Access area 0 accessed as burst ROM (16 consecutive accesses). Can be used only when bus width is 8. Should not be specified when bus width is 16 or 32. 1 Bits 8 and 7--Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode are used, these bits set the number of burst transfers. Bit 8: A5BST1 0 Bit 7: A5BST0 0 1 1 0 Description Access area 5 accessed as ordinary memory (Initial value) Burst access of area 5 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 5 (8 consecutive accesses). Can be used when bus width is 8 or 16. Should not be specified when bus width is 32. Burst access of area 5 (16 consecutive accesses). Can be used only when bus width is 8. Should not be specified when bus width is 16 or 32. 1 Bits 6 and 5--Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode are used, these bits set the number of burst transfers. Rev. 5.00, 09/03, page 237 of 760 Bit 6: A6BST1 0 Bit 5: A6BST0 0 1 Description Access area 6 accessed as ordinary memory (initial value) Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16. Should not be specified when bus width is 32. Burst access of area 6 (16 consecutive accesses). Can be used only when bus width is 8. Should not be specified when bus width is 16 or 32. 1 0 1 Bits 4 to 2--Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Designate the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM, SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description 0 0 0 1 1 0 1 1 0 1 0 1 0 1 Areas 2 and 3 are ordinary memory (Initial value) Reserved (Setting prohibited) Area 2: ordinary memory; area 3: 2 synchronous DRAM* Areas 2 and 3 are synchronous DRAM* *2 Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) 1 Notes: 1. When selecting this mode, set the same bus width for area 2 and area 3. 2. Do not access synchronous DRAM when clock ratio I:B = 1:1 Bit 1--Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as PCMCIA space. Bit 1: A5PCM 0 1 Description Physical space area 5 accessed as ordinary memory Physical space area 5 accessed as PCMCIA space (Initial value) Rev. 5.00, 09/03, page 238 of 760 Bit 0--Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM 0 1 Description Physical space area 6 accessed as ordinary memory Physical space area 6 accessed as PCMCIA space (Initial value) 10.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that selects the bus size of each area and whether an 8-bit port is used or not. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or in standby mode. Do not access external memory outside area 0 until BCR2 register initialization is complete. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 A3SZ1 1 R/W 14 -- 0 R 6 A3SZ0 1 R/W 13 A6SZ1 1 R/W 5 A2SZ1 1 R/W 12 A6SZ0 1 R/W 4 A2SZ0 1 R/W 11 A5SZ1 1 R/W 3 -- 0 R 10 A5SZ0 1 R/W 2 -- 0 R 9 A4SZ1 1 R/W 1 -- 0 R 8 A4SZ0 1 R/W 0 -- 0 R Bits 15, 14, 3, 2, 1, and 0--Reserved: These bits are always read as 0. The write value should always be 0. Bits 2n + 1, 2n--Area n (2-6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus size of physical space area n (n = 2 to 6). Rev. 5.00, 09/03, page 239 of 760 Bit 2n + 1: AnSZ1 0 1 0 1 Bit 2n: AnSZ0 0 1 0 1 0 1 0 1 Port A / B Not used Description Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size Used Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Reserved (Setting prohibited) 10.2.3 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the number of idle (wait) state cycles inserted for each area. For some memories, data bus drive may not be turned off quickly even when the read signal from the external device is turned off. This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. This LSI automatically inserts the number of idle states set in WCR1 in those cases. WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 15 WAITSE L Initial value: R/W: Bit: Initial value: R/W: 0 R/W 7 A3IW1 1 R/W 14 -- 0 R 6 A3IW0 1 R/W 13 A6IW1 1 R/W 5 A2IW1 1 R/W 12 A6IW0 1 R/W 4 A2IW0 1 R/W 11 A5IW1 1 R/W 3 -- 0 R 10 A5IW0 1 R/W 2 -- 0 R 9 A4IW1 1 R/W 1 A0IW1 1 R/W 8 A4IW0 1 R/W 0 A0IW0 1 R/W Rev. 5.00, 09/03, page 240 of 760 Bit 15--WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling timing. Bit 15: WAITSEL 0 1 Description Setting to 1 when using the WAIT signal* Sampled WAIT signal at fall of CKIO (Initial value) Note: * Operation is not guaranteed if WAIT is asserted while WEITSEL = 0. Bits 14, 3, and 2 --Reserved: These bits are always read as 0. The write value should always be 0. Bits 2n + 1, 2n--Area n (6-2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the number of idles inserted between bus cycles when switching between physical space area n (6-2, 0) and another space or between a read access and a write access in the same physical space. Bit 2n + 1: AnIW1 0 1 Bit 2n: AnIW0 0 1 0 1 Description 1 idle cycle inserted 1 idle cycle inserted 2 idle cycles inserted 3 idle cycles inserted (Initial value) 10.2.4 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit readable/writable register that specifies the number of wait state cycles inserted for each area. It also specifies the data access pitch for burst memory accesses. This allows direct connection of even low-speed memories without an external circuit. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 A6 W2 1 R/W 7 A4 W0 1 R/W 14 A6 W1 1 R/W 6 A3 W1 1 R/W 13 A6 W0 1 R/W 5 A3 W0 1 R/W 12 A5 W2 1 R/W 4 A2 W1 1 R/W 11 A5 W1 1 R/W 3 A2 W0 1 R/W 10 A5 W0 1 R/W 2 A0 W2 1 R/W 9 A4 W2 1 R/W 1 A0 W1 1 R/W 8 A4 W1 1 R/W 0 A0 W0 1 R/W Rev. 5.00, 09/03, page 241 of 760 Bits 15 to 13--Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states inserted in physical space area 6. Also specify the number of states for burst transfer. Description First Cycle Bit 15: A6W2 0 Bit 14: A6W1 0 1 1 0 1 Bit 13: A6W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer 2 2 3 4 4 6 8 10 WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 12 to 10--Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states inserted in physical space area 5. Also specify the number of states for burst transfer. Description First Cycle Bit 12: A5W2 0 Bit 11: A5W1 0 1 1 0 1 Bit 10: A5W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer 2 2 3 4 4 6 8 10 WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 5.00, 09/03, page 242 of 760 Bits 9 to 7--Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states inserted in physical space area 4. Description Bit 9: A4W2 0 Bit 8: A4W1 0 1 1 0 1 Bit 7: A4W0 0 1 0 1 0 1 0 1 Inserted Wait State WAIT Pin 0 1 2 3 4 6 8 10 Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled (Initial value) Bits 6 and 5--Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted in physical space area 3. * For Ordinary Memory Description Bit 6: A3W1 0 1 Bit 5: A3W0 0 1 0 1 Inserted Wait States 0 1 2 3 WAIT Pin Ignored Enabled Enabled Enabled (Initial value) * For Synchronous DRAM Description Bit 6: A3W1 0 1 Bit 5: A3W0 0 1 0 1 Synchronous DRAM: CAS Latency 1 1 2 3 (Initial value) Rev. 5.00, 09/03, page 243 of 760 Bits 4 and 3--Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted in physical space area 2. * For Ordinary Memory Description Bit 4: A2W0 0 1 Bit 3: A2W0 0 1 0 1 Inserted Wait States 0 1 2 3 WAIT Pin Ignored Enabled Enabled Enabled (Initial value) * For Synchronous DRAM Description Bit 4: A2W1 0 1 Bit 3: A2W0 0 1 0 1 Synchronous DRAM: CAS Latency 1 1 2 3 (Initial value) Bits 2 to 0--Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states inserted in physical space area 0. Also specify the burst pitch for burst transfer. Description First Cycle Bit 2: A0W2 0 Bit 1: A0W1 0 1 1 0 1 Bit 0: A0W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer 2 2 3 4 4 6 8 10 WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 5.00, 09/03, page 244 of 760 10.2.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit readable/writable register that specifies RAS and CAS timing for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bits TPC1-TPC0, RCD1-RCD0, TRWL1-TRWL0, TRAS1-TRAS0, RASD, and AMX3-AMX0 are written to in the initialization after a power-on reset and should not then be modified again. When RFSH and RMODE are written to, write the same values to the other bits. When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TPC1 0 R/W 7 RASD 0 R/W 14 TPC0 0 R/W 6 AMX3 0 R/W 13 RCD1 0 R/W 5 AMX2 0 R/W 12 RCD0 0 R/W 4 AMX1 0 R/W 11 TRWL1 0 R/W 3 AMX0 0 R/W 10 TRWL0 0 R/W 2 RFSH 0 R/W 9 TRAS1 0 R/W 1 RMODE 0 R/W 8 TRAS0 0 R/W 0 -- 0 R Bits 15 and 14--RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is selected as connected memory, they set the minimum number of cycles until output of the next bank-active command after precharge. However, the number of cycles input immediately after the issue of an all-bank-precharge command (PALL) in the case of an auto-refresh or a precharge command (PRE) in the bank active mode is one fewer than the normal value. TPC1 should not be set to 0 and TPC0 to 1 in the bank active mode. Description Bit 15: TPC1 0 1 Bit 14: TPC0 0 1 0 1 Normal Operation 1 cycle (Initial value) 2 cycles 3 cycles 4 cycles Immediately after Precharge Command* 0 cycle (Initial value) 1 cycle 2 cycles 3 cycles Immediately after Self-Refresh 2 cycles (Initial value) 5 cycles 8 cycles 11 cycles Note: * Immediately after all-bank-precharge (PALL) in the case of an auto-refresh or precharge (PRE) in the bank active mode. Rev. 5.00, 09/03, page 245 of 760 Bits 13 and 12--RAS-CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected as connected memory, these bits set the bank active read/write command delay time. Bit 13: RCD1 0 1 Bit 12: RCD0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles 4 cycles (Initial value) Bits 11 and 10--Write-Precharge Delay (TRWL1, TRWL0): Set the synchronous DRAM write-precharge delay time. This designates the time between the end of a write cycle and the next bank-active command. This setting is valid only when synchronous DRAM is connected. After the write cycle, the next bank-active command is not issued for the period TPC + TRWL. Bit 11: TRWL1 0 1 Bit 10: TRWL0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles Reserved (Setting prohibited) (Initial value) Bits 9 and 8--CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When C R synchronous DRAM interface is selected, no bank-active command is issued during the period TPC + TRAS after an auto-refresh command. Bit 9: TRAS1 0 1 Bit 8: TRAS0 0 1 0 1 Description 2 cycles 3 cycles 4 cycles 5 cycles (Initial value) Bit 7--Synchronous DRAM Bank Active (RASD): Specifies whether synchronous DRAM is used in bank active mode or auto-precharge mode. Set auto-precharge mode when areas 2 and 3 are both designated as synchronous DRAM space. Bit 7: RASD 0 1 Description Auto-precharge mode Bank active mode (Initial value) The bank active mode should not be used unless the bus width for all areas is 32 bits. Rev. 5.00, 09/03, page 246 of 760 Bits 6 to 3--Address Multiplex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexing for synchronous DRAM. For Synchronous DRAM Interface: Bit6: AMX3 1 Bit5: AMX2 1 Bit 4: AMX1 0 Bit 3: AMX0 1 Description The row address begins with A10 (The A10 value is output at A1 when the row address is output. 4M x 16-bit x 4-bank products) The row address begins with A11 (The A11 value is output at A1 when the row address is output. 8M x 16-bit x 4-bank 1 products)* The row address begins with A9 (The A9 value is output at A1 when the row address is output. 1M x 16-bit x 4-bank products) The row address begins with A10 (The A10 value is output at A1 when the row address is output. 2M x 8-bit x 4-bank products, 2M x 16-bit x 4-bank products) The row address begins with A9 (The A9 value is output at A1 when the row address is output. 512k x 32-bit x 4-bank 2 products)* Begin synchronous DRAM access after setting AMX3 to 0 = *1** (Initial value) Reserved (Setting prohibited) 1 0 0 1 0 0 1 1 1 0 0 0 0 Except above value Notes: 1. Can only be set when using a 16-bit bus width. 2. Can only be set when using a 32-bit bus width. Bit 2--Refresh Control (RFSH): The RFSH bit determines whether or not synchronous DRAM refresh operations are is performed. If the refresh function is not used, the timer for generation of periodic refresh requests can also be used as an interval timer. Bit 2: RFSH 0 1 Description No refresh Refresh (Initial value) Rev. 5.00, 09/03, page 247 of 760 Bit 1--Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, an auto-refresh is performed on synchronous DRAM at the period set by refresh-related registers RTCNT, RTCOR, and RTCSR. When a refresh request occurs during an external bus cycle, the refresh cycle is performed after the bus cycle ends. When the RFSH bit is 1 and this bit is also 1, the synchronous DRAM will wait for the end of any executing external bus cycle before going into a self-refresh. All refresh requests to memory that is in the self-refresh state are ignored. Bit 1: RMODE 0 1 Description Auto refresh (RFSH must be 1) Self-refresh (RFSH must be 1) (Initial value) Bit 0--Reserved: This bit is always read as 0. The write value should always be 0. 10.2.6 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the assertion and negation timing of the OE and WE signals for the PCMCIA interface connected to areas 5 and 6. The OE and WE signal assertion width is set by the wait control bits in the WCR2 register. PCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 A6W3 0 R/W 7 0 R/W 14 A5W3 0 R/W 6 0 R/W 13 -- 0 R/W 5 0 R/W 12 -- 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W A5TED2 A6TED2 A5TEH2 A6TEH2 A5TED1 A5TED0 A6TED1 A6TED0 A5TEH1 A5TEH0 A6TEH1 A6TEH0 Rev. 5.00, 09/03, page 248 of 760 Bit 15--Area 6 Wait Control (A6W3): Specifies the number of inserted wait states for area 6 combined with bits A6W2-A6W0 in WCR2. Also specifies the number of transfer states in burst transfer. Clear this bit to 0 when area 6 is not set to PCMCIA. First Cycle Burst Cycle Number of States per One-data Transfer 2 2 3 4 5 7 9 11 13 15 19 23 27 31 35 39 A6W3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6W2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A6W1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A6W0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Inserted Wait States WAIT Pin 0 1 2 3 4 6 8 10 (Initial value) 12 14 18 22 26 30 34 38 Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bit 14--Area 5 Wait Control (A5W3): Specifies the number of inserted wait states for area 5 combined with bits A5W2-A5W0 in WCR2. Also specifies the number of transfer states in burst transfer. Clear this bit to 0 when area 5 is not set to PCMCIA. The relationship between the set value and the number of waits is the same as for A6W3. Bits 13 and 12--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 249 of 760 Bits 11, 7, and 6--Area 5 Address OE/WE Assert Delay (A5TED2, A5TED1, A5TED0): W Specify the delay time from address output to OE/WE assertion for the PCMCIA interface connected to area 5. Bit 11: A5TED2 0 Bit 7: A5TED1 0 1 1 0 1 Bit 6: A5TED0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Bits 10, 5, and 4--Area 6 Address OE/WE Assert Delay (A6TED2, A6TED1, A6TED0): The W A6TED bits specify the delay time from address output to OE/WE assertion for the PCMCIA interface connected to area 6. Bit 10: A6TED2 0 Bit 5: A6TED1 0 1 1 0 1 Bit 4: A6TED0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Rev. 5.00, 09/03, page 250 of 760 Bits 9, 3, and 2--Area 5 OE/WE Negate Address Delay (A5TEH2, A5TEH1, A5TEH0): W Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to area 5. Bit 9: A5TEH2 0 Bit 3: A5TEH1 0 1 1 0 1 Bit 2: A5TEH0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Bits 8, 1, and 0--Area 6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, A6TEH0): W Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to area 6. Bit 8: A6TEH2 0 Bit 1: A6TEH1 0 1 1 0 1 Bit 0: A6TEH0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Rev. 5.00, 09/03, page 251 of 760 10.2.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is an 8-bit write-only register that is written to via the synchronous DRAM address bus. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before accessing the synchronous DRAM. Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area 2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 SDMR address -- -- 7 -- -- W ...................... ...................... 6 -- -- W 5 -- -- W -- -- 4 -- -- W 12 11 -- -- W* 3 -- -- W 10 -- -- W* 2 -- -- W 9 -- -- W 1 -- -- -- 8 -- -- W 0 -- -- -- Note: * Depending on the type of synchronous DRAM. Rev. 5.00, 09/03, page 252 of 760 10.2.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR. Note: The method of writing to RTCSR differs from that for general registers to ensure that RTCSR is not rewritten incorrectly. Use a word transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 10.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 CMF 0 R/W 14 -- 0 R 6 CMIE 0 R/W 13 -- 0 R 5 CKS2 0 R/W 12 -- 0 R 4 CKS1 0 R/W 11 -- 0 R 3 CKS0 0 R/W 10 -- 0 R 2 OVF 0 R/W 9 -- 0 R 1 OVIE 0 R/W 8 -- 0 R 0 LMTS 0 R/W Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--Compare Match Flag (CMF): Indicates that the values of RTCNT and RTCOR match. Bit 7: CMF 0 Description The values of RTCNT and RTCOR do not match (Initial value) Clearing condition: When a refresh is performed after 0 has been written to CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh) 1 The values of RTCNT and RTCOR match Setting condition: RTCNT = RTCOR* Note: * Contents do not change when 1 is written to CMF. Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused when CMF in RTCSR is set to 1. Do not set this bit to 1 when using auto-refresh. Bit 6: CMIE 0 1 Description Interrupt request by CMF is disabled Interrupt request by CMF is enabled (Initial value) Rev. 5.00, 09/03, page 253 of 760 Bits 5 to 3--Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified ratio. RTCOR must be set before setting CKS2-CKS0. Description Bit 5: CKS2 0 Bit 4: CKS1 0 1 1 0 1 Bit 3: CKS0 0 1 0 1 0 1 0 1 Normal external bus clock Clock input disabled Bus clock (CKIO)/4 CKIO/16 CKIO/64 CKIO/256 CKIO/1024 CKIO/2048 CKIO/4096 Bit 2--Refresh Count Overflow Flag (OVF): Indicates when the number of refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in RTCSR. Bit 2: OVF 0 1 Description RFCR has not exceeded the count limit value set in LMTS Clearing condition: When 0 is written to OVF RFCR has exceeded the count limit value set in LMTS Setting condition: When the RFCR value has exceeded the count limit value set in LMTS* Note: * Contents do not change when 1 is written to OVF. (Initial value) Bit 1--Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress generation of interrupt requests by the OVF bit in RTCSR when OVF is set to 1. Bit 1: OVIE 0 1 Description Interrupt request by OVF is disabled Interrupt request by OVF is enabled (Initial value) Rev. 5.00, 09/03, page 254 of 760 Bit 0--Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value in RFCR overflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS 0 1 Description Count limit value is 1024 Count limit value is 512 (Initial value) 10.2.9 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit register containing a readable/writable 8-bit counter that counts up on an input clock. The clock select bits (CKS2-CKS0) in RTCSR select the input clock. When RTCNT matches RTCOR, the CMF bit in RTCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a power-on reset, but continues incrementing after a manual reset. It is not initialized in standby mode, but holds its contents. Note: The method of writing to RTCNT differs from that for general registers to ensure that RTCNT is not rewritten incorrectly. Use a word transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 10.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 -- 7 0 R/W 14 0 -- 6 0 R/W 13 0 -- 5 0 R/W 12 0 -- 4 0 R/W 11 0 -- 3 0 R/W 10 0 -- 2 0 R/W 9 0 -- 1 0 R/W 8 0 -- 0 0 R/W Rev. 5.00, 09/03, page 255 of 760 10.2.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) specifies the upper-limit value of RTCNT. The values of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is a readable/writable register. RTCOR is initialized to H'00 by a power-on reset. It is not initialized by a manual reset or in standby mode, but holds its contents. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR. Note: The method of writing to RTCOR differs from that for general registers to ensure that RTCOR is not rewritten incorrectly. Use a word transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 10.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 -- 7 0 R/W 14 0 -- 6 0 R/W 13 0 -- 5 0 R/W 12 0 -- 4 0 R/W 11 0 -- 3 0 R/W 10 0 -- 2 0 R/W 9 0 -- 1 0 R/W 8 0 -- 0 0 R/W 10.2.11 Refresh Count Register (RFCR) The refresh count register (RFCR) counts the number of refreshing. When RFCR exceeds the count limit value set in the LMTS bit in RTCSR, the OVF bit in RTCSR is set and RFCR is cleared. RFCR is a 10-bit readable/writable counter. RFCR is initialized to H'0000 by a power-on reset. RFCR continues incrementing in a manual reset. It is not initialized by in standby mode, but holds its contents. Note: The method of writing to RFCR differs from that for general registers to ensure that RFCR is not rewritten incorrectly. Use a word transfer instruction to set the six bits starting from the MSB in the upper byte as B'101001, and the remaining bits as the write data. For details, see section 10.2.12, Cautions on Accessing Refresh Control Related Registers. Rev. 5.00, 09/03, page 256 of 760 Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 -- 7 0 R/W 14 0 -- 6 0 R/W 13 0 -- 5 0 R/W 12 0 -- 4 0 R/W 11 0 -- 3 0 R/W 10 0 -- 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W 10.2.12 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5). Perform reads and writes using the following methods: 1. When writing to RFCR, RTCSR, RTCNT, and RTCOR, use only word transfer instructions. Byte transfer instructions cannot be used. When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the write data in the lower byte. When writing to RFCR, place B'101001 in the upper 6 bits and the write data in the remaining bits, as shown in figure 10.5. 2. When reading from RFCR, RTCSR, RTCNT, and RTCOR, carry out reads with a 16-bit width. 0 is read from undefined bits. 15 RTCSR, RTCNT, RTCOR RFCR 1 15 1 0 1 0 0 0 1 0 0 1 0 87 1 Write data 0 Write data 0 10 9 1 Figure 10.5 Writing to RFCR, RTCSR, RTCNT, and RTCOR Rev. 5.00, 09/03, page 257 of 760 10.2.13 MCS0 Control Register (MCSCR0) The MCS0 control register (MCSCR0) is a 16-bit readable/writable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. As the MCS[0] pin is multiplexed as the PTC0 pin, when using the pin as MCS[0], bits PC0MD[1:0] in the PCCR register should be set to 00 (other function). Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 CS2/0 0 R/W 13 -- 0 R 5 CAP1 0 R/W 12 -- 0 R 4 CAP0 0 R/W 11 -- 0 R 3 A25 0 R/W 10 -- 0 R 2 A24 0 R/W 9 -- 0 R 1 A23 0 R/W 8 -- 0 R 0 A22 0 R/W Bits 15 to 7--Reserved: These bits are always read as 0. The write value should always be 0. Bit 6--CS2/CS0 Select (CS2/0): Selects whether an area 2 or area 0 address is to be decoded. Bit 6: CS2/0 0 1 Description Area 0 is selected Area 2 is selected Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7. Bits 5 and 4--Connected Memory Size Specification (CAP1, CAP0) Bit 5: CAP1 0 0 1 1 Bit 4: CAP0 0 1 0 1 Description 32-Mbit memory is connected 64-Mbit memory is connected 128-Mbit memory is connected 256-Mbit memory is connected Bits 3 to 0--Start Address Specification (A25, A24, A23, A22): These bits specify the start address of the memory area for which MCS[0] is asserted. Rev. 5.00, 09/03, page 258 of 760 10.2.14 MCS1 Control Register (MCSCR1) The MCS1 control register (MCSCR1) specifies the MCS[1] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.15 MCS2 Control Register (MCSCR2) The MCS2 control register (MCSCR2) specifies the MCS[2] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.16 MCS3 Control Register (MCSCR3) The MCS3 control register (MCSCR3) specifies the MCS[3] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.17 MCS4 Control Register (MCSCR4) The MCS4 control register (MCSCR4) specifies the MCS[4] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.18 MCS5 Control Register (MCSCR5) The MCS5 control register (MCSCR5) specifies the MCS[5] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.19 MCS6 Control Register (MCSCR6) The MCS6 control register (MCSCR6) specifies the MCS[6] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.20 MCS7 Control Register (MCSCR7) The MCS7 control register (MCSCR7) specifies the MCS[7] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. Rev. 5.00, 09/03, page 259 of 760 10.3 10.3.1 BSC Operation Endian/Access Size and Data Alignment The SH7709S supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a poweron reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high. Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data alignment is done by matching the device's data width and endian. The access unit must also be matched to the device's bus width. This also means that when longword data is read from a byte-width device, four read operations must be performed. In the SH7709S, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 10.7 to 10.12 show the relationship between endian, device data width, and access unit. Table 10.7 32-Bit External Device/Big-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 D31-D24 Data 7-0 -- -- -- Data 15-8 -- Data 31-24 D23-D16 -- Data 7-0 -- -- Data 7-0 -- Data 23-16 D15-D8 -- -- Data 7-0 -- -- Data 15-8 Data 15-8 D7-D0 -- -- -- Data 7-0 -- Data 7-0 Data 7-0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, DQMUU Asserted Asserted Asserted Asserted Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Rev. 5.00, 09/03, page 260 of 760 Table 10.8 16-Bit External Device/Big-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 D31- D24 -- -- -- -- -- -- -- D23- D16 -- -- -- -- -- -- -- -- D15-D8 Data 7-0 -- Data 7-0 -- Data 15-8 Data 15-8 Data 31-24 Data 15-8 D7-D0 -- Data 7-0 -- Data 7-0 Data 7-0 Data 7-0 Data 23-16 Data 7-0 Asserted Asserted Asserted Asserted Asserted WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU Asserted WE0, DQMLL -- Asserted -- Asserted Asserted Asserted Asserted Asserted 2nd time -- at 2 Rev. 5.00, 09/03, page 261 of 760 Table 10.9 8-Bit External Device/Big-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31- D24 -- -- -- -- D23- D16 -- -- -- -- -- -- -- -- -- -- -- -- D15- D8 -- -- -- -- -- -- -- -- -- -- -- -- D7-D0 Data 7-0 Data 7-0 Data 7-0 Data 7-0 Data 15-8 Data 7-0 Data 15-8 Data 7-0 Data 31-24 Data 23-16 Data 15-8 Data 7-0 WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Word access 1st time -- at 0 at 0 2nd time -- at 1 Word access 1st time -- at 2 at 2 2nd time -- at 3 Longword access at 0 1st time -- at 0 2nd time -- at 1 3rd time -- at 2 4th time -- at 3 Rev. 5.00, 09/03, page 262 of 760 Table 10.10 32-Bit External Device/Little-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 D31-D24 -- -- -- Data 7-0 -- Data 15-8 Data 31-24 D23-D16 -- -- Data 7-0 -- -- Data 7-0 Data 23-16 D15-D8 -- Data 7-0 -- -- Data 15-8 -- Data 15-8 D7-D0 Data 7-0 -- -- -- Data 7-0 -- Data 7-0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Asserted Table 10.11 16-Bit External Device/Little-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 D31- D24 -- -- -- -- -- -- -- D23- D16 -- -- -- -- -- -- -- -- D15-D8 -- Data 7-0 -- Data 7-0 Data 15-8 Data 15-8 Data 15-8 Data 31-24 D7-D0 Data 7-0 -- Data 7-0 -- Data 7-0 Data 7-0 Data 7-0 Data 23-16 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Asserted 2nd time -- at 2 Rev. 5.00, 09/03, page 263 of 760 Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 1st time at 0 2nd time at 1 Word access at 2 1st time at 2 2nd time at 3 Longword access at 0 1st time at 0 2nd time at 1 3rd time at 2 4th time at 3 D31- D24 -- -- -- -- -- -- -- -- -- -- -- -- D23- D16 -- -- -- -- -- -- -- -- -- -- -- -- D15-D8 D7-D0 -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 7-0 Data 7-0 Data 7-0 Data 7-0 Data 15-8 Data 7-0 Data 15-8 Data 7-0 Data 15-8 Data 23-16 Data 31-24 WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Rev. 5.00, 09/03, page 264 of 760 10.3.2 Description of Areas Area 0: Area 0 physical address bits A28-A26 are 000. Address bits A31-A29 are ignored and the address range is H'00000000 + H'20000000 x n - H'03FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using external pins MD3 and MD4. When the area 0 space is accessed, the CS0 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A0W2-A0W0 bits in WCR2. When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2-10 according to the number of waits. Area 1: Area 1 physical address bits A28-A26 are 001. Address bits A31-A29 are ignored and the address range is H'04000000 + H'20000000 x n - H'07FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Area 1 is the area specifically for internal peripheral modules. External memories cannot be connected. Control registers of the peripheral modules shown below are mapped to this area 1. Their addresses are physical addresses, to which logical addresses can be mapped when the MMU is enabled: DMAC, PORT, IrDA, SCIF, ADC, DAC, INTC (except INTEVT, IPRA, IPRB) These registers must be set not to be cached by using software. Area 2: Area 2 physical address bits A28-A26 are 010. Address bits A31-A29 are ignored and the address range is H'08000000 + H'20000000 x n - H'0BFFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word, or longword can be selected as the bus width using bits A2SZ1 and A2SZ0 in BCR2 for ordinary memory. When the area 2 space is accessed, the CS2 signal is asserted. When ordinary memories are connected, the RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using bits A2W1 and A2W0 bits in WCR2. Only when ordinary memories are connected, any way can be inserted in each bus cycle by means of the external wait pin (WAIT). When synchronous DRAM is connected, the RAS3U and RAS3L signals, CASU and CASL signals, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RAS3U, RAS3L, CASU, CASL, data timing, and address multiplexing is set with MCR. Rev. 5.00, 09/03, page 265 of 760 Area 3: Area 3 physical address bits A28-A26 are 011. Address bits A31-A29 are ignored and the address range is H'0C000000 + H'20000000 x n - H'0FFFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width using bits A3SZ1 and A3SZ0 bits in BCR2 for ordinary memory. When area 3 space is accessed, CS3 is asserted. When ordinary memories are connected, the RD signal that can be used as OE and the WE0-WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A3W1 and A3W0 bits in WCR2. When synchronous DRAM is connected, the RAS3U and RAS3L signals, CASU and CASL signals, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Area 4: Area 4 physical address bits A28-A26 are 100. Address bits A31-A29 are ignored and the address range is H'10000000 + H'20000000 x n - H'13FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Only ordinary memories such as SRAM and ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using bits A4SZ1 and A4SZ0 in BCR2. When the area 4 space is accessed, the CS4 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A4W2-A4W0 bits in WCR2. Any wait can be inserted in each bus cycle by means of the external wait pin (WAIT). Area 5: Area 5 physical address bits A28-A26 are 101. Address bits A31-A29 are ignored and the address range is the 64 Mbytes at H'14000000 + H'20000000 x n - H'17FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Ordinary memories such as SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range comprises the 32 Mbytes at H'14000000 + H'20000000 x n to H'15FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces), and the I/O card interface address range comprises the 32 Mbytes at H'16000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using bits A5SZ1 and A5SZ0 in BCR2. For the PCMCIA interface, byte or word can be selected as the bus width using bits A5SZ1 and A5SZ0 bits in BCR2. Rev. 5.00, 09/03, page 266 of 760 When the area 5 space is accessed and ordinary memory is connected, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE1 signal are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2-A5W0 bits in WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A5W2- A5W0 bits in WCR2 and the A5W3 bit in PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2-11 (2-39 for the PCMCIA interface) according to the number of waits. The setup and hold times of address/CS5 for the read/write strobe signals can be set in the range 0.5-7.5 using bits A5TED2-A5TED0 and A5TEH2-A5TEH0 in the PCR register. Area 6: Area 6 physical address bits A28-A26 are 110. Address bits A31-A29 are ignored and the address range is the 64 Mbytes at H'18000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). Ordinary memories such as SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range is 32 Mbytes at H'18000000 + H'20000000 x n - H'19FFFFFF + H'20000000 x n and the I/O card interface address range is 32 Mbytes at H'1A000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0-6 and n = 1-6 are the shadow spaces). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using bits A6SZ1 and A6SZ0 in BCR2. For the PCMCIA interface, byte or word can be selected as the bus width using bits A6SZ1 and A6SZ0 in BCR2. When the area 6 space is accessed and ordinary memory is connected, the CS6 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1B signal, CE2B signal, RD signal as OE signal, and WE, ICIORD, and ICIOWR signals are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A6W2-A6W0 bits in WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A6W2- A6W0 bits in WCR2 and the A6W3 bit in PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle is determined within a range of 2-11 (2-39 for the PCMCIA interface) according to the number of waits. The address/CS6 setup and hold times for the read/write strobe signals can be set in the range 0.5-7.5 using bits A6TED2-A6TED0 and A6TEH2-A6TEH0 in the PCR register. Rev. 5.00, 09/03, page 267 of 760 10.3.3 Basic Interface Basic Timing: The basic interface of the SH7709S uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling edge to secure the negation period. Therefore, in case of access at minimum pitch, there is a half-cycle negation period. There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE signal for the byte to be written is asserted. For details, see section 10.3.1, Endian/Access Size and Data Alignment. Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes continuously. The bus is not released during this transfer. For cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. Write-through-area write access and noncacheable read/write access are based on the actual address size. Rev. 5.00, 09/03, page 268 of 760 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 10.6 Basic Timing of Basic Interface Rev. 5.00, 09/03, page 269 of 760 Figures 10.7, 10.8, and 10.9 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k x 8-bit SRAM **** **** **** **** SH7709S A18 A16 A0 CS OE I/O7 **** D24 WE3 D23 **** **** I/O0 WE **** D16 WE2 D15 **** **** **** **** **** D0 WE0 I/O0 WE **** I/O0 WE **** **** I/O0 WE Figure 10.7 Example of 32-Bit Data-Width Static RAM Connection Rev. 5.00, 09/03, page 270 of 760 **** A0 CS OE I/O7 **** A16 **** A0 CS OE I/O7 **** A16 **** D8 WE1 D7 A0 CS OE I/O7 **** **** A16 **** A2 CSn RD D31 SH7709S **** **** **** 128k x 8-bit SRAM **** **** **** A17 A16 A0 CS OE I/O7 **** D8 WE1 D7 **** **** **** I/O0 WE **** D0 WE0 A16 A0 CS OE I/O7 I/O0 WE Figure 10.8 Example of 16-Bit Data-Width Static RAM Connection Rev. 5.00, 09/03, page 271 of 760 **** **** A1 CSn RD D15 SH7709S **** **** **** **** 128k x 8-bit SRAM **** **** A16 A16 A0 CS OE I/O7 I/O0 WE A0 CSn RD D7 **** D0 WE0 Figure 10.9 Example of 8-Bit Data-Width Static RAM Connection Rev. 5.00, 09/03, page 272 of 760 **** Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait State Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 10.10. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 10.10 Basic Interface Wait Timing (Software Wait Only) Rev. 5.00, 09/03, page 273 of 760 When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT signal has no effect if asserted in the T 1 cycle or the first Tw cycle. When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used. However, the WAIT signal is ignored in the following three cases: * A write to external address space in dual address mode with 16-byte DMA transfer * Transfer from an external device with DACK to external address space in single address mode with 16-byte DMA transfer * Cache write-back access Rev. 5.00, 09/03, page 274 of 760 Wait states inserted by WAIT signal T1 Tw Tw Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1) Rev. 5.00, 09/03, page 275 of 760 10.3.4 Synchronous DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2-0) in BCR1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. Note, however, that synchronous DRAM must not be accessed when clock ratio I:B = 1:1. With the SH7709S, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. A data bus width of 16 or 32 bits can be selected. A 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write. The control signals for direct connection of synchronous DRAM are RAS3L, RAS3U, CASL, CASU, RD/WR, CS2 or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed, and is always asserted (high) at other times. In the refresh cycle and mode-register write cycle, RAS3U and RAS3L or CASU and CASL are output. Commands for synchronous DRAM are specified by RAS3L, RAS3U, CASL, CASU, RD/WR, and special address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register write (MRS). Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In littleendian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to address 4n. Figures 10.12 and 10.13 show examples of the connection of two 1M x 16-bit x 4-bank synchronous DRAMs and one 1M x 16-bit x 4-bank synchronous DRAM, respectively. Rev. 5.00, 09/03, page 276 of 760 SH7709S A15 **** **** 64M synchronous DRAM (1M x 16-bit x 4-bank) A13 **** **** **** **** **** A2 CKI0 CKE CSn RAS3x CASx RD/WR D31 **** **** A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML **** **** D16 DQMUU DQMUL D15 **** A13 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML **** **** D0 DQMLU DQMLL Note : "x" is U or L Figure 10.12 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) Rev. 5.00, 09/03, page 277 of 760 SH7709S A14 A13 A12 64M synchronous DRAM (1M x 16 bit x 4 bank) A13 A12 A11 *** *** *** *** *** *** D0 DQMLU DQMLL DQ0 DQMU DQML Figure 10.13 Example of 64-Mbit Synchronous DRAM Connection (16-Bit Bus Width) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX2-AMX0 in MCR. Table 10.13 shows the relationship between the address multiplex specification bits and the bits output at the address pins. A25-A17 and A0 are not multiplexed; the original values are always output at these pins. When A0, the LSB of the synchronous DRAM address, is connected to the SH7709S, it performs longword address specification. Connection should therefore be made in the following order: with a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of the SH7709S, then connect pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of the SH7709S, then connect pin A1 to pin A2. Rev. 5.00, 09/03, page 278 of 760 *** A1 CKIO CKE CSn RAS3x CASx RD/WR D15 A0 CLK CKE CS RAS CAS WE DQ15 *** Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output Setting Bus Memory AMX AMX AMX AMX Output Width Type 3 2 1 0 Timing 32 bits 4M x 1 16bits x 4banks*1 1 0 1 Column address Row address 2M x 0 16bits x 4banks*2 1 0 1 Column address Row address 1M x 0 16bits x 4banks*2 1 0 0 Column address Row address 2M x 0 8bits x 4banks*2 1 0 1 Column address Row address 512k x 0 32bits x 4banks*2 1 1 1 Column address Row address 16 bits 8M x 1 16bits x 4banks*1 1 1 0 Column address Row address 4M x 1 16bits x 4banks*2 1 0 1 Column address Row address A1 to A8 A9 A1 to A9 A8 External Address Pins A10 A11 A12 A13 A14 A15 A16 3 A10 A11 L/H* A13 A23 A24*4 A25*4 A10 to A18 A19 A20 A21 A22 A23 A24*4 A25*4 A17 A1 to A9 A8 3 A10 A11 L/H* A13 A23*4 A24*4 A10 to A18 A19 A20 A21 A22 A23*4 A24*4 A17 A1 to A9 A8 3 A10 A11 L/H* A13 A22*4 A23*4 A9 to A17 A18 A19 A20 A21 A22*4 A23*4 A16 A1 to A9 A8 3 A10 A11 L/H* A13 A23*4 A24*4 A10 to A18 A19 A20 A21 A22 A23*4 A24*4 A17 A1 to A9 A8 3 A10 A11 L/H* A21*4 A22*4 A15 A9 to A17 A18 A19 A20 A21*4 A22*4 A23 A16 A1 to A9 A8 3 A10 L/H* A12 A23 A24*4 A25*4 A11 to A19 A20 A21 A22 A23 A24*4 A25*4 A18 A1 to A9 A8 3 A10 L/H* A12 A22 A23*4 A24*4 A10 to A18 A19 A20 A21 A22 A23*4 A24*4 A17 Rev. 5.00, 09/03, page 279 of 760 Setting Bus Memory AMX AMX AMX AMX Output Width Type 3 2 1 0 Timing 2M x 0 16bits x 4banks*2 1 0 1 Column address Row address 1M x 0 16bits x 4banks*2 1 0 0 Column address Row address 2M x 0 8bits x 4banks*2 1 0 1 Column address Row address A1 to A8 A9 A1 to A9 A8 External Address Pins A10 A11 A12 A13 A14 A15 A16 3 A10 L/H* A12 A22*4 A23*4 A24 A10 to A18 A19 A20 A21 A22*4 A23*4 A24 A17 A1 to A9 A8 3 A10 L/H* A12 A21*4 A22*4 A15 A 9 to A17 A18 A19 A20 A21*4 A22*4 A23 A16 A1 to A9 A8 3 A10 L/H* A12 A22*4 A23*4 A24 A10 to A18 A19 A20 A21 A22*4 A23*4 A24 A17 Notes: 1. Only RAL3L or CASL is output. 2. When addresses are upper 32 Mbytes, RAS3U or CASU is output. When addresses are lower 32 Mbytes, RAS3L or CASL is output. 3. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 4. Bank address specification Rev. 5.00, 09/03, page 280 of 760 Table 10.14 Example of Correspondence between SH7709S and Synchronous DRAM Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width)) SH7709S Address Pin RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A0 CAS Cycle A23 A22 A13 L/H A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A13(BA1) A12(BA0) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used Address Address precharge setting Address Synchronous DRAM Address Pin Function BANK select bank address Burst Read: In the example in figure 10.15 it is assumed that four 2M x 8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted at the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In the SH7709S, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval. The example in figure 10.14 shows the basic cycle. To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the RCD bits in MCR, with values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles Rev. 5.00, 09/03, page 281 of 760 independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Tpc Figure 10.14 Basic Timing for Synchronous DRAM Burst Read Rev. 5.00, 09/03, page 282 of 760 Figure 10.15 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1-Td4 in a synchronous DRAM cycle. When a burst read is performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16 bytes, address updating is performed for A3 and A2 only (when the bus width is 16 bits, address updating is performed for A3, A2, and A1). The order of access is as follows: in a fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3x CASx RD/WR DQMxx Trw Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Tpc D31 to D0 BS Figure 10.15 Synchronous DRAM Burst Read Wait Specification Timing Rev. 5.00, 09/03, page 283 of 760 Single Read: Figure 10.16 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3x Tc1 Td1 Tpc CASx RD/WR DQMxx D31 to D0 BS Figure 10.16 Basic Timing for Synchronous DRAM Single Read Rev. 5.00, 09/03, page 284 of 760 Burst Write: The timing chart for a burst write is shown in figure 10.17. In the SH7709S, a burst write occurs only in the event of cache write-back or 16-byte DMAC transfer. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs autoprecharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is deferred during this interval. The number of Trwl cycles can be specified by the TRWL bits in MCR. Rev. 5.00, 09/03, page 285 of 760 Tr CKIO Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) Address upper bits A12, A11, A10 or A9 Address lower bits CSn RD/WR RAS3x CASx DQMxx D31 to D0 (read) BS Figure 10.17 Basic Timing for Synchronous DRAM Burst Write Rev. 5.00, 09/03, page 286 of 760 Single Write: The basic timing chart for write access is shown in figure 10.18. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is deferred during this interval. The number of Trwl cycles can be specified by the TRWL bits in MCR. Rev. 5.00, 09/03, page 287 of 760 Tr CKIO Tc1 (Trwl) (Tpc) Address upper bits A12 or A10 Address lower bits CSn RD/WR RAS3x CASx DQMxx D31 to D0 BS CKE Figure 10.18 Basic Timing for Synchronous DRAM Single Write Rev. 5.00, 09/03, page 288 of 760 Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command, in the same way as in the RAS down state in DRAM fast page mode. As synchronous DRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance of the precharge command and the row address strobe command is determined by the TPC bits in MCR. Whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address (P1), and the average number of cycles from completion of one access to the next access (Ta). If Ta is greater than Tpc, the delay due to the precharge wait when writing is imperceptible. In this case, the access speed for bank active mode and basic access is determined by the number of cycles from the start of access to issuance of the read/write command: (Tpc + Trcd) x (1 - P1) and Trcd, respectively. There is a limit on Tras, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of Tras. In this way, it is possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 10.19, a burst read cycle for the same row address in figure 10.20, and a burst read cycle for different row addresses in figure 10.21. Similarly, a burst write cycle without auto-precharge is shown in figure 10.22, a burst write cycle for the same row address in figure 10.23, and a burst write cycle for different row addresses in figure 10.24. Rev. 5.00, 09/03, page 289 of 760 A Tnop cycle, in which no operation is performed, is inserted before the Tc cycle in which the READ command is issued in figure 10.20, but when synchronous DRAM is read, there is a twocycle latency for the DQMxx signal that performs the byte specification. If the Tc cycle were performed immediately, without inserting a Tnop cycle, it would not be possible to perform the DQMxx signal specification for Td1 cycle data output. This is the reason for inserting the Tnop cycle. If the CAS latency is two cycles or longer, Tnop cycle insertion is not performed, since the timing requirements will be met even if the DQMxx signal is set after the Tc cycle. When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 10.19 or 10.22, followed by repetition of the cycle in figure 10.20 or 10.23. An access to a different area 3 space during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 10.21 or 10.24 is executed instead of that in figure 10.20 or 10.23. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. The bank active mode should not be used unless the bus width for all areas is 32 bits. Rev. 5.00, 09/03, page 290 of 760 Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.19 Burst Read Timing (No Precharge) Rev. 5.00, 09/03, page 291 of 760 Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.20 Burst Read Timing (Same Row Address) Rev. 5.00, 09/03, page 292 of 760 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.21 Burst Read Timing (Different Row Addresses) Rev. 5.00, 09/03, page 293 of 760 Tr Tc1 Tc2 Tc3 Tc4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.22 Burst Write Timing (No Precharge) Rev. 5.00, 09/03, page 294 of 760 Tc1 Tc2 Tc3 Tc4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.23 Burst Write Timing (Same Row Address) Rev. 5.00, 09/03, page 295 of 760 Tp Tr Tc1 Tc2 Tc3 Td4 CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 BS Figure 10.24 Burst Write Timing (Different Row Addresses) Rev. 5.00, 09/03, page 296 of 760 Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. * Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2-0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2CKS0 setting. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.25 shows the auto-refresh cycle timing. All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by the TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must be set so as to satisfy the synchronous DRAM refresh cycle time stipulation (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset. Rev. 5.00, 09/03, page 297 of 760 RTCOR value RTCNT RTCNT cleared to 0 when RTCNT = RTCOR H'00000000 RTCSR.CKS(2 to 0) CMF CMF flag cleared by start of refresh cycle External bus = 000 000 Time Auto-refresh cycle Figure 10.25 Auto-Refresh Operation Rev. 5.00, 09/03, page 298 of 760 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U, RAS3L CASU, CASL RD/WR Figure 10.26 Synchronous DRAM Auto-Refresh Timing Rev. 5.00, 09/03, page 299 of 760 * Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh timing is shown in figure 10.27. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7709S's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. When using synchronous DRAM, use the following procedure to initiate self-refreshing. 1. Clear the refresh control bit to 0. 2. Write H'00 to the RTCNT register. 3. Set the refresh control bit and refresh mode bit to 1. Rev. 5.00, 09/03, page 300 of 760 Tp TRs1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO CKE CSn RAS3U, RAS3L CASU, CASL RD/WR Figure 10.27 Synchronous DRAM Self-Refresh Timing * Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus right occurs that is longer than the refresh interval. When a refresh request is generated, the IRQOUT pin is asserted (driven low). Therefore, normal refreshing can be performed by having the IRQOUT pin monitored by a bus master other than the SH7709S requesting the bus, or the bus arbiter, and returning the bus to the SH7709S. When refreshing is started, and if no other interrupt request has been generated, the IRQOUT pin is negated (driven high). Rev. 5.00, 09/03, page 301 of 760 Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by the SH7709S, arbitrary data is written in a byte-size access to the following addresses. With 32-bit bus width: CAS latency 1 CAS latency 2 CAS latency 3 With 16-bit bus width: CAS latency 1 CAS latency 2 CAS latency 3 Area 2 FFFFD420 FFFFD440 FFFFD460 Area 3 FFFFE420 FFFFE440 FFFFE460 Area 2 FFFFD840 FFFFD880 FFFFD8C0 Area 3 FFFFE840 FFFFE880 FFFFE8C0 Mode register setting timing is shown in figure 10.28. As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks (PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued in the TMw1 cycle. Address signals, when the mode-register write command is issued, are as follows: 32-bit bus width: A15-A9 = 0000100 (burst read and single write) A8-A6 = CAS latency A5 = 0 (burst type = sequential) A4-A2 = 000 (burst length 1) 16-bit bus width: A14-A8 = 0000100 (burst read and single write) A7-A5 = CAS latency A4 = 0 (burst type = sequential) A3-A1 = 000 (burst length 1) Rev. 5.00, 09/03, page 302 of 760 Before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is usually achieved automatically while various kinds of initialization are being performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for autorefreshing is not initialized, and so the cycle must always be an auto-refresh cycle. TRp1 CKIO A15 to A13 or A15 to A12 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 A11 A12 or A10 A9 to A2 CSn RD/WR RAS3U or RAS3L CASU or CASL D31 to D0 CKE (High) Figure 10.28 Synchronous DRAM Mode Write Timing Rev. 5.00, 09/03, page 303 of 760 10.3.5 Burst ROM Interface Setting bits A0BST1-0, A5BST1-0, and A6BST1-0 in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 10.29. Two wait cycles are set. Basically, access is performed in the same way as for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits A0BST1-0, A5BST1-0, or A6BST1-0. When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is connected, only 4 can be set. WAIT pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 10.30. However, the WAIT signal is ignored in the following three cases: * A write to external address space in dual address mode with 16-byte DMA transfer * Transfer from an external device with DACK to external address space in single address mode with 16-byte DMA transfer * Cache write-back access Rev. 5.00, 09/03, page 304 of 760 T1 CKIO TW TW TB2 TB1 TW TB2 TB1 T2 A25 to A4 A3 to A0 CSn RD/WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.29 Burst ROM Wait Access Timing Rev. 5.00, 09/03, page 305 of 760 T1 CKIO TB2 TB1 TB2 TB1 TB2 TB1 T2 A25 to A4 A3 to A0 CSn RD/WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.30 Burst ROM Basic Access Timing Rev. 5.00, 09/03, page 306 of 760 10.3.6 PCMCIA Interface In the SH7709S, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2. When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and A5SZ0, or A6SZ1 and A6SZ0, in BCR2. Figure 10.31 shows an example of PCMCIA card connection to the SH7709S. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the SH7709S's bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the PCMCIA interface for the SH7709S in big-endian mode is stipulated independently. However, the WAIT signal is ignored in the following three cases: * A write to external address space in dual address mode with 16-byte DMA transfer * Transfer from an external device with DACK to external address space in single address mode with 16-byte DMA transfer * Cache write-back access Rev. 5.00, 09/03, page 307 of 760 A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A D7 to D0 G DIR D15 to D8 G DIR G A25 to A0 D15 to D0 PC card (memory/IO) SH7709S RD WE1 ICIORD ICIOWR WAIT IOIS16 G CE1 CE2 OE WE/PGM (IORD) (IOWR) WAIT (IOIS16) Card detection circuit CD1, CD2 Output port D7 to D0 A25 to A0 G D15 to D0 G DIR D15 to D8 G DIR PC card (memory/IO) CE1 CE2 OE WE/PGM G WAIT Card detection circuit CD1, CD2 Figure 10.31 Example of PCMCIA Interface Rev. 5.00, 09/03, page 308 of 760 Memory Card Interface Basic Timing: Figure 10.32 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses. With a high external bus frequency (CKIO), the setup and hold times for the address (A24-A0), card enable (CS5, CE2A, CS6, CE2B), and write data (D15-D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in the SH7709S). The SH7709S provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also, software waits by means of a WCR2 register setting and hardware waits by means of the WAIT pin can be inserted in the same way as for the basic interface. Figure 10.33 shows the PCMCIA memory bus wait timing. Rev. 5.00, 09/03, page 309 of 760 Tpcm1 Tpcm2 CKIO A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) BS Figure 10.32 Basic Timing for PCMCIA Memory Card Interface Rev. 5.00, 09/03, page 310 of 760 Tpcm0 CKIO Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) BS WAIT Figure 10.33 Wait Timing for PCMCIA Memory Card Interface Rev. 5.00, 09/03, page 311 of 760 Memory Card Interface Burst Timing: In the SH7709S, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc. Burst access mode timing is shown in figures 10.34 and 10.35. Tpcm1 CKIO Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 A25 to A4 A3 to A0 CExx RD/WR RD (read) D15 to D0 (read) BS Figure 10.34 Basic Timing for PCMCIA Memory Card Interface Burst Access Rev. 5.00, 09/03, page 312 of 760 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 CExx RD/WR RD (read) D15 to D0 (read) BS WAIT Figure 10.35 Wait Timing for PCMCIA Memory Card Interface Burst Access Rev. 5.00, 09/03, page 313 of 760 When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16 Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal. 32-Mbyte capacity (REG = I/O port) Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 Common memory/ attribute memory I/O space Common memory/ attribute memory I/O space Up to 16-Mbyte capacity (REG = A24) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 10.36 PCMCIA Space Allocation Rev. 5.00, 09/03, page 314 of 760 I/O Card Interface Timing: Figures 10.37 and 10.38 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6, the bus access is automatically performed as an I/O card interface access when a physical address from H'1A000000 to H'1BFFFFFF is accessed. When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU. When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for are 5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Figure 10.39 shows the basic timing for dynamic bus sizing. In big-endian mode, the IOIS16 signal is not supported, and should be fixed low. Rev. 5.00, 09/03, page 315 of 760 Tpci1 Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS Figure 10.37 Basic Timing for PCMCIA I/O Card Interface Rev. 5.00, 09/03, page 316 of 760 Tpci0 CKIO Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 10.38 Wait Timing for PCMCIA I/O Card Interface Rev. 5.00, 09/03, page 317 of 760 Tpci0 CKIO Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w A25 to A1 A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 10.39 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 5.00, 09/03, page 318 of 760 10.3.7 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. This results in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write. If there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. There are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from the SH7709S. When the SH7709S performs consecutive write cycles, the data transfer direction is fixed (from the SH7709S to other memory) and there is no problem. With read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. Bits AnIW1 and AnIW0 (n = 0, 2-6) in WCR1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when the SH7709S performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes. Rev. 5.00, 09/03, page 319 of 760 T1 CKIO A25 to A0 CSm CSn BS RD/WR RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 10.40 Waits between Access Cycles 10.3.8 Bus Arbitration When a bus release request (BREQ) is asserted from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not released during burst transfers for cache fills or write-back, or TAS instruction execution between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is restarted. See Appendix A.1, Pin States, for the pin states when the bus is released. The SH7709S sometimes needs to retrieve a bus it has released. For example, when memory generates a refresh request or an interrupt request internally, the SH7709S must perform the appropriate processing. The SH7709S has a bus request signal (IRQOUT) for this purpose. When it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus. The SH7709S retrieves the bus and carries out the processing. Rev. 5.00, 09/03, page 320 of 760 IRQOUT Pin Assertion Conditions: * When a memory refresh request has been generated but the refresh cycle has not yet begun * When an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (I3-I0) in the status register (SR). (This does not depend on the SR.BL bit.) 10.3.9 Bus Pull-Up With the SH7709S, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted. Figure 10.41 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not in use. The data pin pull-up timing for a read cycle is shown in figure 10.42, and the timing for a write cycle in figure 10.43. CKIO A25 to A0 Pull-up Hi-Z BACK Figure 10.41 Pull-Up Timing for Pins A25 to A0 Rev. 5.00, 09/03, page 321 of 760 CKIO D31 to D0 Pull-up Pull-up RD CSn Figure 10.42 Pull-Up Timing for Pins D31 to D0 (Read Cycle) CKIO D31 to D0 Pull-up Pull-up WEn CSn Figure 10.43 Pull-Up Timing for Pins D31 to D0 (Write Cycle) Rev. 5.00, 09/03, page 322 of 760 10.3.10 MCS[0] to MCS[7] Pin Control The SH7709S is provided with pins MCS[0]-MCS[7] as dedicated CS pins for the ROM connected to area 0 or 2. Assertion of MCS[0]-MCS[7] is controlled by settings in MCSCR0- MCSCR7. This enables 32-, 64-, 128-, or 256-Mbit memory to be connected to area 0 or area 2. However, only CS2/0 = 0 (area 0) should be used for MCSCR0. Table 10.15 shows MCSCR0- MCSCR7 settings and MCS[0]-MCS[7] assertion conditions. As the MCS[0]-MCS[7] pins are multiplexed as the PTC0-PTC7 pins, when using these pins as MCS[0]-MCS[7], the corresponding bits in the PCCR register should be set to "other function." When CS2/0 = 0 in the MCSCR0 and when the PTC0 pin is switched to MCS[0] (when PCOMD1-PCOMD0 are set to "other function"), the CS0 pin is also switched to MCS[0]. As port register writes operate on the peripheral clock, they take time compared with instruction execution by the CPU operating on the high-speed internal clock. Therefore, if an instruction that accesses MCS[1] to MCS[7] is located several instructions after an instruction that switches port C to MCS, the switch from PTC[n] to MCSn and from CS0 to MCS[0] may not be performed correctly. To prevent this problem, the following switching procedure should be used. * When the program runs with cache on (1) To switch port C to MCS, set the corresponding bits in the PCCR register to 00 ("other function"). (2) Read the PCCR register and check whether the set value is read. Repeat until the set value is read. (3) Perform a dummy read from non-cacheable CS0 space (e.g. address H'A0000000). This will result in an access to the CS0 space, and immediately afterward, CS0 will be switched to MCS[0], and port C[n] will be switched to MCS[n]. (4) Access can now be made to the MCS[1] to MCS[7] spaces. * When the program runs in MCS[0] space with cache off (1) Set the PCCR register as in (1) above. (2) Place at least three NOP instructions after the instruction in (1). As a result, when the PCCR register is rewritten, an access to the CS0 space will be generated, and immediately afterward, CS0 will be switched to MCS[0], and port C[n] will be switched to MCS[n]. (3) Access can now be made to the MCS[1] to MCS[7] spaces. Rev. 5.00, 09/03, page 323 of 760 Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0-7) MCSCRx Settings CS2/0 CAP1 CAP0 A25 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A24 -- -- 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A23 -- -- -- -- -- -- 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CS0 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L MCS[x] Assertion Conditions CS2 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Address Bus A [25:0] Notes H'0000000 to H'1FFFFFF 256-Mbit ROM H'2000000 to H'3FFFFFF H'0000000 to H'0FFFFFF 128-Mbit ROM H'1000000 to H'1FFFFFF H'2000000 to H'2FFFFFF H'3000000 to H'3FFFFFF H'0000000 to H'07FFFFF 64-Mbit ROM H'0800000 to H'0FFFFFF H'1000000 to H'17FFFFF H'1800000 to H'1FFFFFF H'2000000 to H'27FFFFF H'2800000 to H'2FFFFFF H'3000000 to H'37FFFFF H'3800000 to H'3FFFFFF H'0000000 to H'03FFFFF 32-Mbit ROM H'0400000 to H'07FFFFF H'0800000 to H'0BFFFFF H'0C00000 to H'0FFFFFF H'1000000 to H'13FFFFF H'1400000 to H'17FFFFF H'1800000 to H'1BFFFFF H'1C00000 to H'1FFFFFF H'2000000 to H'23FFFFF H'2400000 to H'27FFFFF H'2800000 to H'2BFFFFF H'2C00000 to H'2FFFFFF H'3000000 to H'33FFFFF H'3400000 to H'37FFFFF H'3800000 to H'3BFFFFF H'3C00000 to H'3FFFFFF Rev. 5.00, 09/03, page 324 of 760 MCSCRx Settings CS2/0 CAP1 CAP0 A25 1 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A24 -- -- 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A23 -- -- -- -- -- -- 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CS0 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H MCS[x] Assertion Conditions CS2 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L Address Bus A[25:0] Notes H'0000000 to H'1FFFFFF 256-Mbit ROM H'2000000 to H'3FFFFFF H'0000000 to H'0FFFFFF 128-Mbit ROM H'1000000 to H'1FFFFFF H'2000000 to H'2FFFFFF H'3000000 to H'3FFFFFF H'0000000 to H'07FFFFF 64-Mbit ROM H'0800000 to H'0FFFFFF H'1000000 to H'17FFFFF H'1800000 to H'1FFFFFF H'2000000 to H'27FFFFF H'2800000 to H'2FFFFFF H'3000000 to H'37FFFFF H'3800000 to H'3FFFFFF H'0000000 to H'03FFFFF 32-Mbit ROM H'0400000 to H'07FFFFF H'0800000 to H'0BFFFFF H'0C00000 to H'0FFFFFF H'1000000 to H'13FFFFF H'1400000 to H'17FFFFF H'1800000 to H'1BFFFFF H'1C00000 to H'1FFFFFF H'2000000 to H'23FFFFF H'2400000 to H'27FFFFF H'2800000 to H'2BFFFFF H'2C00000 to H'2FFFFFF H'3000000 to H'33FFFFF H'3400000 to H'37FFFFF H'3800000 to H'3BFFFFF H'3C00000 to H'3FFFFFF Rev. 5.00, 09/03, page 325 of 760 Rev. 5.00, 09/03, page 326 of 760 Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. 11.1.1 Features The DMAC has the following features. * Four channels * 4-GB address space in the architecture * 16-byte transfer (In 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) * Choice of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length * 16 Mbytes (16,777,216 transfers) * Address mode: Dual address mode and single address mode are supported. In addition, direct address transfer mode or indirect address transfer mode can be selected. Dual address mode transfer: Both the transfer source and transfer destination are accessed by address. Dual address mode has direct address transfer mode and indirect address transfer mode. Direct address transfer mode: The values specified in the DMAC registers indicates the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: Data is transferred with the address stored prior to the address specified in the transfer source address in the DMAC. Other operations are the same as those of direct address transfer mode. This function is only available in channel 3. Four bus cycles are required for one data transfer. Single address mode transfer: Either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. One transfer unit of data is transferred in one bus cycle. * Channel functions: The transfer mode that can be specified depends on the channel: Channel 0: External request can be accepted. Channel 1: External request can be accepted. Channel 2: This channel has a source address reload function, which reloads a source address every four transfers. Rev. 5.00, 09/03, page 327 of 760 Channel 3: In this channel, direct address mode or indirect address transfer mode can be specified. * Reload function: The value that was specified in the source address register can be automatically reloaded every four DMA transfers. This function is only available in channel 2. * Transfer requests External request (From two DREQ pins (channels 0 and 1 only). DREQ can be detected either by the falling edge or by low level.) On-chip module request (Requests from on-chip peripheral modules such as serial communications interface (IrDA and SCIF), A/D converter (A/D) and a timer (CMT). This request can be accepted in all the channels.) Auto request (The transfer request is generated automatically within the DMAC.) * Selectable bus modes: Cycle-steal mode or burst mode * Selectable channel priority levels: Fixed mode: The channel priority is fixed. Round-robin mode: The priority of the channel in which the execution request was accepted is made the lowest. * Interrupt request: An interrupt request to the CPU can be generated after the specified number of transfers. Rev. 5.00, 09/03, page 328 of 760 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the DMAC. DMAC module Iteration control Register control Peripheral bus Internal bus SARn DARn On-chip peripheral module DMATCRn Start-up control CHCRn DREQ0, DREQ1 IrDA, SCIF A/D converter CMT DEIn DACK0, DACK1 DRAK0, DRAK1 External ROM External RAM External I/O (memory mapped) External I/O (with acknowledge) Bus state controller DMAOR Request priority control Bus interface Legend DMAOR: DMAC operation register DMAC source address register SARn: DMAC destination address register DARn: DMATCRn: DMAC transfer count register CHCRn: DMAC channel control register DMA transfer-end interrupt request to DEIn: CPU n = 0 to 3 Figure 11.1 Block Diagram of DMAC Rev. 5.00, 09/03, page 329 of 760 11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.1 DMAC Pins Channel 0 Name DMA transfer request DMA transfer request acceptance DMA request acknowledge 1 DMA transfer request DMA transfer request acceptance DMA request acknowledge Symbol DREQ0 DACK0 I/O I O Function DMA transfer request input from external device to channel 0 Strobe output to an external I/O upon DMA transfer request from external device to channel 0 Output showing that DREQ0 has been accepted DMA transfer request input from external device to channel 1 Strobe output to an external I/O upon DMA transfer request from external device to channel 1 Output showing that DREQ1 has been accepted DRAK0 DREQ1 DACK1 O I O DRAK1 O Rev. 5.00, 09/03, page 330 of 760 11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 registers: each channel has four registers, and one overall DMAC control register. Table 11.2 DMAC Registers Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 Abbreviation SAR0 DAR0 DMATCR0 CHCR0 SAR1 DAR1 DMATCR1 CHCR1 SAR2 DAR2 DMATCR2 CHCR2 R/W R/W R/W R/W Initial Value Address Undefined Undefined Undefined H'04000020 (H'A4000020)*4 H'04000024 (H'A4000024)*4 H'04000028 (H'A4000028)*4 Register Access Size Size 32 32 24 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 R/W*1 H'00000000 R/W R/W R/W Undefined Undefined Undefined H'0400002C 32 (H'A400002C)*4 H'04000030 (H'A4000030)*4 H'04000034 (H'A4000034)*4 H'04000038 (H'A4000038)*4 32 32 24 R/W*1 H'00000000 R/W R/W R/W Undefined Undefined Undefined H'0400003C 32 (H'A400003C)*4 H'04000040 (H'A4000040)*4 H'04000044 (H'A4000044)*4 H'04000048 (H'A4000048)*4 32 32 24 R/W*1 H'00000000 H'0400004C 32 (H'A400004C)*4 Rev. 5.00, 09/03, page 331 of 760 Channel Name 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Shared Abbreviation SAR3 DAR3 DMATCR3 CHCR3 R/W R/W R/W R/W Initial Value Address Undefined Undefined Undefined H'04000050 (H'A4000050)*4 H'04000054 (H'A4000054)*4 H'04000058 (H'A4000058)*4 Register Access Size Size 32 32 24 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 8, 16*2 R/W*1 H'00000000 R/W*1 H'0000 H'0400005C 32 (H'A400005C)*4 H'04000060 (H'A4000060)*4 16 DMA operation register DMAOR Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to bit 1 of CHCR0 to CHCR3, and bits 1 and 2 of DMAOR to clear the flag after 1 is read. 2. If 16-bit access is used on SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3, the value in the 16 bits that were not accessed is retained. 3. DMATCR comprises the 24 bits from bit 0 to bit 23. The upper 8 bits, bits 24 to 31, cannot be written with 1 and are always read as 0. 4. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 332 of 760 11.2 11.2.1 Register Descriptions DMA Source Address Registers 0-3 (SAR0-SAR3) DMA source address registers 0-3 (SAR0-SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. Operation is not guaranteed if other addresses are specified. An undefined value will be returned in a reset. The previous value is retained in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 23 -- R/W 30 -- R/W 22 -- R/W 29 -- R/W 21 -- R/W 28 -- R/W 20 -- R/W 27 -- R/W 26 -- R/W ... ... ... ... -- R/W 25 -- R/W 24 -- R/W 0 Rev. 5.00, 09/03, page 333 of 760 11.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers include a count function, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16-bit or 32-bit units, make sure to specify a destination address with a 16-byte boundary (16n address). An undefined value will be returned in a reset. The previous value is retained in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 23 -- R/W 30 -- R/W 22 -- R/W 29 -- R/W 21 -- R/W 28 -- R/W 20 -- R/W 27 -- R/W 26 -- R/W ... ... ... ... -- R/W 25 -- R/W 24 -- R/W 0 Rev. 5.00, 09/03, page 334 of 760 11.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) DMA transfer count registers 0-3 (DMATCR0-DMATCR3) are 24-bit readable/writable registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, and 16,777,216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining number of transfers. In 16-byte transfer, one 16-byte transfer (128 bits) is counted as one. Writing to upper eight bits in DMATCR is invalid; 0s are read if these bits are read. The write value should always be 0. An undefined value will be returned in a reset. The previous value is retained in standby mode. Bit: Initial value: R/W: 31 -- R 30 -- R 29 -- R 28 -- R 27 -- R 26 -- R 25 -- R 24 -- R Bit: Initial value: R/W: 23 -- R/W 22 -- R/W 21 -- R/W 20 -- R/W ... ... ... ... 0 -- R/W Rev. 5.00, 09/03, page 335 of 760 11.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMA channel control registers 0-3 (CHCR0-CHCR3) are 32-bit readable/writable registers that specify the operation mode, transfer method, etc., for each channel. Bit 20 is only used in CHCR3; it is not used in CHCR0 to CHCR2. Consequently, writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. Bit 19 is only used in CHCR2; it is not used in CHCR0, CHCR1, and CHCR3. Consequently, writing to this bit is invalid in CHCR0, CHCR1, and CHCR3; 0 is read if this bit is read. Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1; they are not used in CHCR2 and CHCR3. Consequently, writing to these bits is invalid in CHCR2 and CHCR3; 0s are read if these bits are read. These register values are initialized to 0 in a reset. The previous value is retained in standby mode. Bit: Initial value: R/W: 31 -- 0 R ... ... ... ... 21 -- 0 R 20 DI 0 19 RO 18 RL 17 AM 16 AL 0 0 0 0 *2 (R/W)*2 (R/W)*2 (R/W)*2 (R/W)*2 (R/W) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 DM1 0 R/W 7 -- 0 R 14 DM0 0 R/W 6 DS 0 (R/W)* 2 13 SM1 0 R/W 5 TM 0 R/W 12 SM0 0 R/W 4 TS1 0 R/W 11 RS3 0 R/W 3 TS0 0 R/W 10 RS2 0 R/W 2 IE 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W)* 1 8 RS0 0 R/W 0 DE 0 R/W Notes: 1. Only 0 can be written to the TE bit after 1 is read. 2. The DI, RO, RL, AM, AL, and DS bits are not included in some channels. Rev. 5.00, 09/03, page 336 of 760 Bits 31 to 21--Reserved: These bits are always read as 0. The write value should always be 0. Bit 20--Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in channel 3. This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. The write value should always be 0. When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if indirect address mode is specified. Bit 20: DI 0 1 Description Direct address mode operation for channel 3 Indirect address mode operation for channel 3 (Initial value) Bit 19--Source Address Reload Bit (RO): Selects whether the source address initial value is reloaded in channel 2. This bit is only valid in CHCR2. Writing to this bit is invalid in CHCR0, CHCR1, and CHCR3; 0 is read if this bit is read. The write value should always be 0. When using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. Operation is not guaranteed if reloading is specified. Bit 19: RO 0 1 Description Source address is not reloaded Source address is reloaded (Initial value) Bit 18--Request Check Level Bit (RL): Specifies whether DRAK (DREQ acknowledge) signal output is active-high or active-low. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0. Bit 18: RL 0 1 Description Active-low DRAK output Active-high DRAK output (Initial value) Rev. 5.00, 09/03, page 337 of 760 Bit 17--Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle or in the data write cycle in dual address mode. DACK is always output in single address mode, regardless of this bit specification. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0. Bit 17: AM 0 1 Description DACK output in read cycle DACK output in write cycle (Initial value) Bit 16--Acknowledge Level (AL): Specifies whether DACK (acknowledge) signal output is active-high or active-low. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0. Bit 16: AL 0 1 Description Active-low DACK output Active-high DACK output (Initial value) Bits 15 and 14--Destination Address Mode Bits 1 and 0 (DM1, DM0): Select whether the DMA destination address is incremented, decremented, or left fixed. Bit 15: DM1 0 0 1 Bit 14: DM0 0 1 0 Description Fixed destination address (Initial value) Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) Setting prohibited 1 1 Rev. 5.00, 09/03, page 338 of 760 Bits 13 and 12--Source Address Mode Bits 1 and 0 (SM1, SM0): Select whether the DMA source address is incremented, decremented, or left fixed. Bit 13: SM1 0 0 1 Bit 12: SM0 0 1 0 Description Fixed source address (Initial value) Source address is incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Source address is decremented (-1 in 8-bit transfer, -2 in 16bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) Setting prohibited 1 1 If the transfer source is specified by indirect address, specify the address holding the value of the address in which the data to be transferred is stored (i.e. the indirect address) in source address register 3 (SAR3). Specification of SAR3 incrementing or decrementing in indirect address mode depends on the SM1 and SM0 settings. In this case, however, the SAR3 increment or decrement value is +4, -4, or fixed at 0, regardless of the transfer data size specified in TS1 and TS0. Rev. 5.00, 09/03, page 339 of 760 Bits 11 to 8--Resource Select Bits 3 to 0 (RS3 to RS0): Specify which transfer requests will be sent to the DMAC. Bit 11: RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 10: RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 9: RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 8: RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description External request*, dual address mode Setting prohibited External request / Single address mode External address space external device with DACK External request / Single address mode External device with DACK external address space Auto request Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited IrDA transmission IrDA reception SCIF transmission SCIF reception A/D converter CMT (Initial value) Notes: When using 16-byte transfer, the following settings must not be made: 1010 IrDA transmission 1011 IrDA reception 1100 SCIF transmission 1101 SCIF reception 1110 A/D converter 1111 CMT Operation is not guaranteed if these settings are made. * External request specification is valid only in channels 0 and 1. None of the request sources can be selected in channels 2 and 3. Rev. 5.00, 09/03, page 340 of 760 Bit 6--DREQ Select Bit (DS): Selects low-level or falling-edge detection as the sampling method D for the DREQ pin used in external request mode. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3; 0 is read if this bit is read. The write value should always be 0. In channels 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an auto-request is specified, the specification of this bit is ignored and falling-edge detection is fixed except in an auto-request. Bit 6: DS 0 1 Description DREQ detected by low level DREQ detected at falling edge (Initial value) Bit 5--Transmit Mode (TM): Specifies the bus mode when transferring data. Bit 5: TM 0 1 Description Cycle-steal mode Burst mode (Initial value) Bits 4 and 3--Transmit Size Bits 1 and 0 (TS1, TS0): Specify the size of data to be transferred. Bit 4: TS1 0 0 1 1 Bit 3: TS0 0 1 0 1 Description Byte size (8 bits) Word size (16 bits) Longword size (32 bits) 16-byte unit (4 longword transfers) (Initial value) Bit 2--Interrupt Enable Bit (IE): If this bit is set to 1, an interrupt is requested on completion of the number of data transfers specified in DMATCR (i.e. when TE = 1). Bit 2: IE 0 1 Description Interrupt request is not generated on completion of data transfers specified in DMATCR (Initial value) Interrupt request is generated on completion of data transfers specified in DMATCR Rev. 5.00, 09/03, page 341 of 760 Bit 1--Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. Bit 1: TE 0 Description Data transfers specified in DMATCR not completed Clearing conditions: Writing 0 to TE after reading TE = 1 Power-on reset, manual reset 1 Data transfers specified in DMATCR completed (Initial value) Bit 0--DMAC Enable Bit (DE): Enables operation of the corresponding channel. Bit 0: DE 0 1 Description Channel operation disabled Channel operation enabled (Initial value) If an auto-request is specified (RS3 to RS0), transfer starts when this bit is set to 1. In an external request or an internal module request, transfer starts when a transfer request is generated after this bit is set to 1. Clearing this bit during transfer terminates the transfer. Even if the DE bit is set, transfer is not enabled if the TE bit is 1, the DME bit in DMAOR is 0, or the NMIF or AE bit in DMAOR is 1. Rev. 5.00, 09/03, page 342 of 760 11.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the DMAC transfer mode. These register values are initialized to 0 in a reset. The previous value is retained in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 AE 0 R/(W)* 9 PR1 0 R/W 1 NMIF 0 R/(W)* 8 PR0 0 R/W 0 DME 0 R/W Note: * Only 0 can be written to the AE and NMIF bits after 1 is read. Bits 15 to 10--Reserved: These bits are always read as 0. The write value should always be 0. Bits 9 and 8--Priority Mode Bits 1 and 0 (PR1, PR0): Select the priority level between channels when there are simultaneous transfer requests for multiple channels. Bit 9: PR1 0 0 1 1 Bit 8: PR0 0 1 0 1 Description CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 Round-robin (Initial value) Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 343 of 760 Bit 2--Address Error Flag Bit (AE): Indicates that an address error occurred by the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE 0 Description No DMAC address error; DMA transfer is enabled Clearing conditions: Writing 0 to AE after reading AE = 1 Power-on reset, manual reset 1 DMAC address error; DMA transfer is disabled This bit is set by occurrence of a DMAC address error (Initial value) Bit 1--NMI Flag Bit (NMIF): Indicates that an NMI is input. This bit is set regardless of whether the DMAC is in the operating or halted state. The CPU cannot write 1 to this bit. Only 0 can be written to clear this bit after 1 is read. Bit 1: NMIF 0 Description No NMI input; DMA transfer is enabled Power-on reset, manual reset 1 NMI input; DMA transfer is disabled This bit is set by occurrence of an NMI interrupt (Initial value) Clearing conditions: Writing 0 to NMIF after reading NMIF = 1 Bit 0--DMA Master Enable Bit (DME): Enables or disables the DMAC on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is enabled on the corresponding channel. If this bit is cleared during transfer, transfer on all the channels will be terminated. Even if the DME bit is set, transfer is not enabled if the TE bit is 1 or the DE bit is 0 in CHCR, or the NMIF or AE bit is 1 in DMAOR. Bit 0: DME 0 1 Description DMA transfer disabled on all channels DMA transfer enabled on all channels (Initial value) Rev. 5.00, 09/03, page 344 of 760 11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The dual address mode has direct address transfer mode and indirect address transfer mode. Burst mode or cycle-steal mode can be selected as the bus mode. 11.3.1 DMA Transfer Flow After the DMA source address register (SAR), DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (according to the TS0 and TS1 settings). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs by the DMAC or an NMI interrupt is generated, the transfer is aborted. Figure 11.2 is a flowchart of this procedure. Rev. 5.00, 09/03, page 345 of 760 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and AE, NMIF, TE = 0? Yes No Transfer request?*1 Yes No *2 *3 Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated DMATCR = 0? Yes No AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Yes Transfer aborted No DEI interrupt request (when IE = 1) Does AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Yes Transfer end No Normal end Notes: 1. In auto-request mode, transfer begins when AE, NMIF, and TE are both 0 and the DE and DME bits are set to 1. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. Figure 11.2 DMAC Transfer Flowchart Rev. 5.00, 09/03, page 346 of 760 11.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The request mode is selected in the RS3-RS0 bits of DMA channel control registers 0-3 (CHCR0-CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bit of CHCR0-CHCR3 and the DME bit of DMAOR are set to 1, the transfer begins so long as the TE bit of CHCR0-CHCR3 and the NMIF and AE bits of DMAOR are 0. External Request Mode: In this mode a transfer is performed in response to the request signal (DREQ) of an external device. Choose one of the modes shown in table 11.3 according to the application system. When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Choose DREQ detection by either a falling edge or low level of the signal input with the DS bit in CHCR0 and CHCR1 (DS = 0 for level detection, DS = 1 for edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 11.3 Selecting External Request Modes with RS Bits RS3 0 RS2 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Any* External memory, memory-mapped external device External device with DACK Destination Any* External device with DACK External memory, memory-mapped external device 1 Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (This applies only to IrDA, SCIF, A/D converter, D/A converter, and I/O ports.) On-Chip Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) of an on-chip module. This mode cannot be set in case of 16-byte transfer. These are six transfer request signals: the receive-data-full interrupts (RXI) and the transmit-data-empty interrupts (TXI) from two serial communication interfaces (IrDA, SCIF), the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer interrupt (CMI) of the CMT (table 11.4). When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon input of a transfer Rev. 5.00, 09/03, page 347 of 760 request signal. The source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the data transfer source must be the A/D data register (ADDR). Table 11.4 Selecting On-Chip Peripheral Module Request Modes with RS3-0 Bits DMA Transfer Request RS3 RS2 RS1 RS0 Source 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 DestiDMA Transfer Request Signal Source nation Bus Mode Any* RDR1 TDR1 Any* TDR2 Any* Any* Any* Cycle-steal Cycle-steal Cycle-steal Cycle-steal Cycle-steal Burst/ cycle-steal IrDA TXI1 (IrDA transmit-data-empty transmitter interrupt transfer request) IrDA receiver RXI1 (IrDA receive-data-full interrupt transfer request) SCIF TXI2 (SCIF transmit-data-empty Any* transmitter interrupt transfer request) SCIF receiver A/D converter CMT RXI2 (SCIF receive-data-full interrupt transfer request) ADI (A/D conversion end interrupt) CMI (Compare match timer interrupt) RDR1 ADDR Any* ADDR: A/D data register of A/D converter Note: * External memory, memory-mapped external device, on-chip peripheral module (This applies only to IrDA, SCIF, A/D converter, D/A converter, and I/O ports.) When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request signal, an interrupt is not sent to the CPU. The DMA transfer request signals in table 11.4 are automatically discontinued when the corresponding DMA transfer is performed. If cycle-steal mode is being employed, they are withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last transfer. Rev. 5.00, 09/03, page 348 of 760 11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority order of the channels remain fixed. There are three kinds of fixed modes as follows: CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 These are selected by the PR1 and PR0 bits in DMAOR. Round-Robin Mode: Each time one word, byte, or longword is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 11.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset. Rev. 5.00, 09/03, page 349 of 760 (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 CH1 > CH2 > CH3 > CH0 Channel 0 becomes lowestpriority. Priority order after transfer (2) When channel 1 transfers Channel 1 becomes lowestpriority. The priority of channel 0, which was higher than channel 1, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH2 > CH3 > CH0 > CH1 (3) When channel 2 transfers Channel 2 becomes lowestpriority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately Priority order CH3 > CH0 > CH1 > CH2 after there is a request to transfer after transfer channel 1 only, channel 1 becomes lowest-priority and the priority of channels 3 and 0, which were Post-transfer priority order higher than channel 1, is also when there is an CH2 > CH3 > CH0 > CH1 shifted. immediate transfer request to channel 1 only CH0 > CH1 > CH2 > CH3 Initial priority order (4) When channel 3 transfers Priority order after transfer Priority order after transfer CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 Priority order does not change. Figure 11.3 Round-Robin Mode Rev. 5.00, 09/03, page 350 of 760 Figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 0 and 3. 2. Channel 0 has a higher priority than channel 3, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest-priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest-priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest-priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 (3) Channel 1 3 (2) Channel 0 transfer start Priority order changes 0>1>2>3 1,3 (4) Channel 0 transfer ends (5) Channel 1 transfer starts 1>2>3>0 3 (6) Channel 1 transfer ends Priority order changes 2>3>0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3 Figure 11.4 Changes in Channel Priority in Round-Robin Mode Rev. 5.00, 09/03, page 351 of 760 11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. Dual address mode has a direct address mode and indirect address mode. In direct address mode, an output address value is the data transfer target address; in indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. Data transfer timing depends on the bus mode, which may be cycle-steal mode or burst mode. Table 11.5 Supported DMA Transfers Destination External Device with DACK Not available Dual, single Dual, single Not available External Memory Dual, single Dual Dual Dual MemoryMapped External Device Dual, single Dual Dual Dual On-Chip Peripheral Module Not available Dual Dual Dual Source External device with DACK External memory Memory-mapped external device On-chip peripheral module Notes: 1. 2. 3. 4. Dual: Dual address mode Single: Single address mode Dual address mode includes direct address mode and indirect address mode. 16-byte transfer is not available for on-chip peripheral modules. Address Modes: * Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. Dual address mode has (1) a direct address transfer mode and (2) an indirect address transfer mode. Rev. 5.00, 09/03, page 352 of 760 (1) In direct address transfer mode, DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 11.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Figure 11.6 shows an example of the timing at this time. DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is an address, and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 11.5 Operation of Direct Address Mode in Dual Address Mode Rev. 5.00, 09/03, page 353 of 760 CKIO Transfer source address A25 to A0 Transfer destination address CSn D31 to D0 RD WEn DACKn Data read cycle (1st cycle) Data write cycle (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) (2) In indirect address transfer mode, the address of memory in which data to be transferred is stored is specified in the transfer source address register (SAR3) in the DMAC. Consequently, in this mode, the address value specified in the transfer source address register in the DMAC is read first. This value is temporarily stored in the DMAC. Next, the read value is output as an address, and the value stored in that address is stored in the DMAC again. Then, the value read afterwards is written to the address specified in the transfer destination address; this completes one DMA transfer. 16-byte transfer is not possible. Figure 11.7 shows an example. In this example, the transfer destination, the transfer source, and the storage destination of the indirect address are 16-bit external memories, and transfer data is 16 or 8 bits. Figure 11.8 shows an example of the transfer timing. Rev. 5.00, 09/03, page 354 of 760 SAR3 D M A C DAR3 Temporary buffer Data buffer Address bus Memory Data bus Transfer source module Transfer destination module When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address. If data bus connected to an external memory space is 16 bits wide, two bus cycles are necessary. First and second bus cycles SAR3 Address bus Memory Data bus D M A C DAR3 Temporary buffer Data buffer Transfer source module Transfer destination module When the value in the temporary buffer is an address, the data is read from the transfer source module to the data buffer. Third bus cycle SAR3 Address bus Memory Data bus D DAR3 M A Temporary buffer C Data buffer Transfer source module Transfer destination module When the value in SAR3 is an address, the value in the data buffer is written to the transfer source module. Fourth bus cycle Note: This example shows memory, the transfer source module, and the transfer destination module; in practice, any module can be connected in the addressing space. Figure 11.7 Indirect Address Operation in Dual Address Mode (When External Memory Space has a 16-Bit Width) Rev. 5.00, 09/03, page 355 of 760 CKIO A25 to A0 Transfer source address (H) Transfer source address (L) Indirect address Transfer destination address NOP CSn D31 to D0 Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer RD WEn Indirect address (H) Indirect address (L) Indirect address Transfer data Transfer data Transfer source address *1 NOP Transfer source address *2 Transfer data Indirect address Transfer data Transfer data Address read cycle NOP cycle Data read cycle (3rd) Data write cycle (4th) (1st) (2nd) External memory space external memory space (external memory is 16-bit width) Notes: 1. The internal address bus value does not change, and is controlled by the port. 2. The DMAC does not fetch the value until 32-bit data is output to the internal data bus. Figure 11.8 Example of Transfer Timing in the Indirect Address Mode in Dual Address Mode Rev. 5.00, 09/03, page 356 of 760 * Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 11.9, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus SH7709S DMAC External memory External data bus External device with DACK DACK DREQ Data flow Figure 11.9 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figures 11.10 and 11.11 show examples of DMA transfer timing in single address mode. Rev. 5.00, 09/03, page 357 of 760 CKIO A25 to A0 CSn WE D31 to D0 DACKn BS (a) External device with DACK CKIO A25 to A0 CSn RD D31 to D0 DACKn BS Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK Address output to external memory space external memory space (ordinary memory) Write strobe signal to external memory space Address output to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (b) External memory space (ordinary memory) external device with DACK Figure 11.10 Example of DMA Transfer Timing in Single Address Mode Rev. 5.00, 09/03, page 358 of 760 CKIO A25 to A0 CSn D31 to D0 RD WEn Transfer source address +4 +8 +12 DACKn Figure 11.11 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer, External Memory Space (Ordinary Memory) External Device with DACK) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR0-CHCR3. * Cycle-Steal Mode In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (byte, word, longword, or 16-byte unit) DMAC. When another transfer request occurs, the bus is obtained from the other bus master and transfer is performed for one transfer unit. When that transfer ends, the bus is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In the cycle-steal mode, transfer areas are not affected regardless of the transfer request source, transfer source, and transfer destination settings. Figure 11.12 shows an example of DMA transfer timing in cycle-steal mode. Transfer conditions shown in the figure are: Dual address mode DREQ level detection Rev. 5.00, 09/03, page 359 of 760 DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC CPU Read Write CPU Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode * Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Burst mode cannot be used when a serial communication interface (IrDA, SCI), or A/D converter is the transfer request source. Figure 11.13 shows an example of burst mode timing. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write CPU Figure 11.13 Example of Transfer in Burst Mode Rev. 5.00, 09/03, page 360 of 760 Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.6 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Dual Transfer Category External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memorymapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Request Mode External External All* 1 Bus Mode B/C B/C B/C B/C B/C Transfer Size (Bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 Usable Channels 0,1 0, 1 0-3* 0-3* 0-3* 5 All * All * 1 5 1 5 All * All * 2 B/C* B/C* B/C* B/C B/C 3 8/16/32* 8/16/32* 8/16/32* 4 0-3* 0-3* 0-3* 0, 1 0, 1 5 2 3 4 5 On-chip peripheral module and on- All * chip peripheral module Single External device with DACK and external memory External device with DACK and memory-mapped external device 2 3 4 5 External External 8/16/32/128 8/16/32/128 B: Burst, C: Cycle-steal Notes: 1. External requests, auto requests and on-chip peripheral module (CMT) requests are all available. 2. External requests, auto requests and on-chip peripheral module requests are all available. When the IrDA, SCIF, or A/D converter is also the transfer request source, however, the transfer destination or transfer source must be the IrDA, SCIF, or A/D converter, respectively. 3. If the transfer request source is the IrDA, SCIF, or A/D converter only cycle-steal mode is available. 4. The access size permitted when the transfer destination or source is an on-chip peripheral module register. 5. If the transfer request is an external request, only channels 0 and 1 are available. Rev. 5.00, 09/03, page 361 of 760 Bus Mode and Channel Priority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle-steal mode or burst mode. If the priority is set in round-robin mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is in cycle-steal mode or burst mode. The bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. Even if the priority is set in fixed mode or in round-robin mode, the bus will not be given to the CPU since channel 1 is in burst mode. This example is illustrated in figure 11.14. CPU DMAC CH1 DMAC CH1 DMAC CH0 CH0 DMAC CH1 CH1 DMAC CH0 CH0 DMAC CH1 DMAC CH1 CPU CPU DMAC CH1 Burst mode Round-robin mode in DMAC CH0 and CH1 DMAC CH1 Burst mode CPU Priority: Round-robin mode CH0: Cycle-steal mode CH1: Burst mode Figure 11.14 Bus State when Multiple Channels Are Operating Rev. 5.00, 09/03, page 362 of 760 11.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 10, Bus State Controller (BSC). DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled by clock pulse (CKIO) falling edge or low level detection. When DREQ input is detected, a DMAC bus cycle is generated and DMA transfer performed, at the earliest, three states later. The second and subsequent DREQ sampling operations are started two cycles after the first sample. Operation * Cycle-Steal Mode In cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or edge detection is used. For example, in figure 11.15 (cycle-steal mode, level input), DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. If DREQ is not detected at this time, sampling is performed in each subsequent cycle. Thus, DREQ sampling is performed one step in advance. The third sampling operation is not performed until the idle cycle following the end of the first DMA transfer. The above conditions are the same whatever the number of CPU transfer cycles, as shown in figure 11.16. The above conditions are also the same whatever the number of DMA transfer cycles, as shown in figure 11.17. DACK is output in a read in the example in figure 11.15, and in a write in the example in figure 11.16. In both cases, DACK is output for the same duration as CSn. Figure 11.18 shows an example in which sampling is executed in all subsequent cycles when DREQ cannot be detected. Rev. 5.00, 09/03, page 363 of 760 * Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ sampling timing is the same as in cycle-steal mode. For example, in figure 11.20, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. Subsequent sampling operations are performed in the idle cycle following the end of the DMA transfer cycle. In burst mode, also, the DACK output period is the same as in cycle-steal mode. * Burst Mode, Edge Detection In the case of burst mode with edge detection, DREQ sampling is only performed once. For example, in figure 11.21, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. After this, DMAC transfer is executed continuously until the number of data transfers set in the DMATCR register have been completed. DREQ is not sampled during this time. To restart DMAC after it has been suspended by an NMI, first clear NMIF, then input an edge request again. In burst mode, also, the DACK output period is the same as in cycle-steal mode. Rev. 5.00, 09/03, page 364 of 760 3rd sampling 2nd sampling 1st sampling CKIO Bus cycle DREQ CPU DRAK DACK Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) DMAC(R) DMAC(W) CPU DMAC(R) DMAC(W) Rev. 5.00, 09/03, page 365 of 760 3rd sampling 2nd sampling 1st sampling CKIO DREQ CPU DRAK Bus cycle DACK Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) Rev. 5.00, 09/03, page 366 of 760 DMAC(R) DMAC(W) CPU DMAC(R) 3rd sampling 1st sampling 2nd sampling DRAK (High output) DREQ CPU DACK (RD output) CKIO Bus cycle Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) DMAC(R) DMAC(W) CPU DMAC(W) Rev. 5.00, 09/03, page 367 of 760 Rev. 5.00, 09/03, page 368 of 760 2nd sampling is performed, but since DREQ is high, per-cycle sampling starts 3rd sampling is performed, but since DREQ is high, per-cycle sampling starts 1st sampling CKIO DREQ DRAK 2nd sampling 3rd sampling Bus cycle CPU DMAC(R) DACK (RD output) DMAC(W) CPU DMAC(R) DMAC(W) Figure 11.18 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) CPU 2nd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 3rd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 1st sampling CKIO 2nd sampling 3rd sampling DREQ High High DRAK High High Bus cycle CPU DMAC(R) DACK (RD output) DMAC(W) CPU DMAC(R) DMAC(W) CPU Figure 11.19 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point. Rev. 5.00, 09/03, page 369 of 760 Rev. 5.00, 09/03, page 370 of 760 1st sampling CKIO DREQ DRAK Bus cycle DACK CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) 2nd sampling 3rd sampling Figure 11.20 Burst Mode, Level Input DMAC(R) 1st sampling CKIO DREQ DRAK Bus cycle DACK CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) Figure 11.21 Burst Mode, Edge Input Rev. 5.00, 09/03, page 371 of 760 11.3.6 Source Address Reload Function Channel 2 includes a reload function, in which the value is returned to the value set in the source address register (SAR2) every four transfers by setting the RO bit in CHCR2 to 1. 16-byte transfer cannot be used. Figure 11.22 shows this operation. Figure 11.23 shows a timing chart for the source address reload function under the following conditions: burst mode, auto-request, 16-bit transfer data size, SAR2 incremented, DAR2 fixed, reload function on, and use of channel 2 only. DMAC DMAC control RO bit = 1 CHCR2 Reload control Reload signal SAR2 (initial value) Reload signal 4 time count SAR2 Figure 11.22 Source Address Reload Function Diagram Rev. 5.00, 09/03, page 372 of 760 Address bus Transfer request Count signal DMATCR2 CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data First transfer on channel 2 SAR2 output DAR2 output Second transfer SAR2+2 output DAR2 output Third transfer SAR2+4 output DAR2 output Fourth transfer SAR2+6 output DAR2 output Fifth transfer SAR2 reload SAR2 output DAR2 output Figure 11.23 Timing Chart of Source Address Reload Function The reload function can be executed with a transfer data size of 8, 16, or 32 bits. DMATCR2, which specifies the transfer count, decrements 1 each time a transfer ends regardless of whether the reload function is on or off. Consequently, a multiple of four must be specified in DMATCR2 when the reload function is on. Operation is not guaranteed if other values are specified. The counter that counts the execution of four transfers for the address reload function is reset by clearing the DME bit in DMAOR or the DE bit in CHCR2, by setting the transfer end flag (TE bit in CHCR2), by DMAC address error, and by NMI input, as well as by a reset, but the SAR2, DAR2, and DMATCR2 registers are not reset. Therefore, if these sources are generated, there will be a mix of an initialized counter and uninitialized registers in the DMAC, and a malfunction will be caused by restarting the DMAC in that state. Consequently, if one of these sources other than setting of the TE bit occurs during use of the address reload function, set SAR2, DAR2, and DMATCR2 again. Rev. 5.00, 09/03, page 373 of 760 11.3.7 DMA Transfer Ending Conditions The DMA transfer ending conditions are different for ending on an individual channel and ending on all channels together. At the end of transfer, the following conditions are applied except in the case where the value set in the DMA transfer count register (DMATCR) reaches 0. (a) Cycle-steal mode (external request, internal request, and auto-request) When the transfer ending conditions are satisfied, DMAC transfer request acceptance is suspended. The DMAC stops operating after completing the number of transfers that it has accepted until the ending conditions are satisfied. In cycle-steal mode, the operation is the same regardless of whether the transfer request is detected by level or edge. (b) Burst mode, edge detection (external request, internal request, and auto-request) The timing from the point where the ending conditions are satisfied to the point where the DMAC stops operating is the same as in cycle-steal mode. With edge detection in burst mode, though only one transfer request is generated to start the DMAC, stop request sampling is performed at the same timing as transfer request sampling in cycle-steal mode. As a result, the period when a stop request is not sampled is regarded as the period when a transfer request is generated, and after performing the DMA transfer for this period, the DMAC stops operating. (c) Burst mode, level detection (external request) Same as in (a). (d) Bus timing when transfer is suspended Transfer is suspended when one transfer ends. Even if transfer ending conditions are satisfied during a read in direct address transfer in dual address mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, DMAC operation is suspended. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (DMATCR) is 0, or when the DE bit in the channel's CHCR register is cleared to 0. * When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. This transfer ending does not apply to (a) to (d) described above. * When DE in CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR register. The TE bit is not set when this happens. This transfer ending applies to (a) to (d) described above. Rev. 5.00, 09/03, page 374 of 760 Conditions for Ending on All Channels Simultaneously: Transfers on all channels end (1) when the AE or NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME bit in DMAOR is cleared to 0. * Transfer ending when the NMIF bit is set to 1 in DMAOR: When an NMI interrupt occurs, the AE or NMIF bit is set to 1 in DMAOR and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus to an other bus master. Consequently, even if the AE or NMI bit is set to 1 during transfer, SAR, DAR, DMATCR are updated. The TE bit is not set. To resume transfer after NMI interrupt exception handling, clear the NMIF bit to 0. At this time, if there are channels that should not be restarted, clear the corresponding DE bit in CHCR. * Transfer ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR forcibly aborts transfer on all channels. The TE bit is not set. All channels abort their transfer according to the conditions in (a) to (d) in section 11.3.7, DMA Transfer Ending Conditions, as in NMI interrupt generation. In this case, the values in SAR, DAR, and DMATCR are also updated. Rev. 5.00, 09/03, page 375 of 760 11.4 11.4.1 Compare Match Timer (CMT) Overview The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The CMT has a 16-bit counter. Features The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (P/4, P/8, P/16, P/64) can be selected. * Generates a DMA transfer request when compare match occurs. Block Diagram Figure 11.24 shows a block diagram of the CMT. P/4 P/8 P/16 P/64 CMT Control circuit Clock selection Comparator CMCOR0 CMCSR0 CMCNT0 CMSTR Module bus Bus interface Internal bus CMSTR: CMCSR0: CMCOR0: CMCNT0: Compare match timer start register Compare match timer control/status register 0 Compare match timer constant register 0 Compare match timer counter 0 Figure 11.24 Block Diagram of CMT Rev. 5.00, 09/03, page 376 of 760 Register Configuration Table 11.7 summarizes the CMT register configuration. Table 11.7 Register Configuration Name Compare match timer start register Compare match timer control/status register 0 Compare match counter 0 Compare match constant register 0 Abbreviation CMSTR CMCSR0 CMCNT0 CMCOR0 R/W R/(W) R/(W)* R/W R/W 1 Initial Value H'0000 H'0000 H'0000 H'FFFF Address Access Size (Bits) H'04000070 8, 16, 32 2 (H'A4000070)* H'04000072 8, 16, 32 2 (H'A4000072)* H'04000074 8, 16, 32 2 (H'A4000074)* H'04000076 8, 16, 32 2 (H'A4000076)* Notes: 1. The only value that can be written to the CMF bit in CMCSR0 is 0 to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. 11.4.2 Register Descriptions Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether compare match counter 0 (CMCNT0) is operated or halted. It is initialized to H'0000 by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R/W 8 -- 0 R 0 STR0 0 R/W Bits 15 to 2--Reserved: These bits are always read as 0. The write value should alway be 0. Bit 1--Reserved: This bit can be read or written. The write value should always be 0. Rev. 5.00, 09/03, page 377 of 760 Bit 0--Count Start 0 (STR0): Selects whether to operate or halt CMCNT0. Bit 0: STR0 0 1 Description CMCNT0 count operation halted CMCNT0 count operation (Initial value) Compare Match Timer Control/Status Register 0 (CMCSR0) The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 CMF 0 R/(W)* 14 -- 0 R 6 -- 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W Note: * The only value that can be written is 0 to clear the flag. Bits 15 to 8 and 5 to 2--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--Compare Match Flag (CMF): Indicates whether or not the compare match timer counter 0 (CMCNT0) and compare match timer constant 0 (CMCOR0) values match. Bit 7: CMF 0 1 Description CMCNT0 and CMCOR0 values do not match Clearing condition: Write 0 to CMF after reading CMF = 1 CMCNT0 and CMCOR0 values match (Initial value) Rev. 5.00, 09/03, page 378 of 760 Bit 6--Reserved: This bit can be read or written. The wite value should always be 0. Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): Select the clock input to CMCNT from among the four internal clocks obtained by dividing the system clock (P). When the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the clock selected by CKS1 and CKS0. Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description P /4 P /8 P /16 P /64 (Initial value) Compare Match Counter 0 (CMCNT0) Compare match counter 0 (CMCNT0) is a 16-bit register used as an up-counter. When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on that clock. When the CMCNT0 value matches that of compare match constant register 0 (CMCOR0), CMCNT0 is cleared to H'0000 and the CMF flag in CMCSR0 is set to 1. CMCNT0 is initialized to H'0000 by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W Rev. 5.00, 09/03, page 379 of 760 Compare Match Constant Register 0 (CMCOR0) Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare match period. CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 1 R/W 14 1 R/W 6 1 R/W 13 1 R/W 5 1 R/W 12 1 R/W 4 1 R/W 11 1 R/W 3 1 R/W 10 1 R/W 2 1 R/W 9 1 R/W 1 1 R/W 8 1 R/W 0 1 R/W 11.4.3 Operation Period Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the selected clock. When the CMCNT counter value matches that of CMCOR0, the CMCNT0 counter is cleared to H'0000 and the CMF flag in the CMCSR0 register is set to 1. The CMCNT0 counter begins counting up again from H'0000. Figure 11.25 shows the compare match counter operation. CMCNT0 value CMCOR0 Counter cleared by CMCOR0 compare match H'0000 Time Figure 11.25 Counter Operation Rev. 5.00, 09/03, page 380 of 760 CMCNT0 Count Timing One of four clocks (P/4, P/8, P/16, P/64) obtained by dividing the P clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows the timing. CK Internal clock CMCNT0 input clock CMCNT0 N-1 N N+1 Figure 11.26 Count Timing 11.4.4 Compare Match Compare Match Flag Setting Timing The CMF bit in the CMCSR0 register is set to 1 by the compare match signal generated when the CMCOR0 register and the CMCNT0 counter match. The compare match signal is generated in the final state of the match (timing at which the CMCNT0 counter matching count value is updated). Consequently, after the CMCOR0 register and the CMCNT0 counter match, a compare match signal will not be generated until a CMCNT0 counter input clock occurs. Figure 11.27 shows the CMF bit setting timing. Rev. 5.00, 09/03, page 381 of 760 CK CMCNT0 input clock CMCNT0 N 0 CMCOR0 N Compare match signal CMF CMI Figure 11.27 CMF Setting Timing Compare Match Flag Clearing Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle T1 T2 CK CMF Figure 11.28 Timing of CMF Clearing by the CPU Rev. 5.00, 09/03, page 382 of 760 11.5 11.5.1 Examples of Use Example of DMA Transfer between On-Chip IrDA and External Memory In this example, receive data of the on-chip IrDA is transferred to external memory using DMAC channel 3. Table 11.8 shows the transfer conditions and register settings. In addition, it is recommended that the trigger for the number of receive FIFO data bytes in IrDA be set to 1 (RTRG1 = RTRG0 = 0 in SCFCR). Table 11.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory Transfer Conditions Transfer source: RDR1 of on-chip IrDA Transfer destination: External memory Number of transfers: 64 Transfer source address: Fixed Transfer destination address: Incremented Transfer request source: IrDA (RXI1) Bus mode: Cycle-steal Transfer unit: Byte Interrupt request generated at end of transfer Channel priority order: 0 > 2 > 3 > 1 DMAOR H'0101 Register SAR3 DAR3 DMATCR3 CHCR3 Setting H'0400014A H'00400000 H'00000040 H'00004B05 Rev. 5.00, 09/03, page 383 of 760 11.5.2 Example of DMA Transfer between A/D Converter and External Memory In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with the address reload function on. Table 11.9 shows the transfer conditions and register settings. Table 11.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory Transfer Conditions Transfer source: On-chip A/D converter Transfer destination: Internal memory Number of transfers: 128 (reloading 32 times) Transfer source address: Incremented Transfer destination address: Decremented Transfer request source: A/D converter Bus mode: Burst Transfer unit: Longword Interrupt request generated at end of transfer Channel priority order: 0 > 2 > 3 > 1 DMAOR H'0101 Register SAR2 DAR2 DMATCR2 CHCR2 Setting H'04000080 H'00400000 H'00000080 H'00089E35 When the address reload function is on, the value set in SAR returns to the initially set value every four transfers. In this example, when a transfer request is generated from the A/D converter, byte data is read from the register at address H'04000080 in the A/D converter, and is written to external memory address H'00400000. Since longword data has been transferred, the values in SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus is kept and data transfers are performed successively because this transfer is in burst mode. After four transfers end, fifth and sixth transfers are performed if the address reload function is off, and the value in SAR is incremented from H'0400008C to H'04000090, H'04000094... If the address reload function is on, DMA transfer stops after the fourth transfer ends, and the bus request signal to the CPU is cleared. At this time, the value stored in SAR is not incremented from H'0400008C to H'04000090, but returns to the initially set value, H'04000080. The value in DAR continues to be decremented regardless of whether the address reload function is on or off. Rev. 5.00, 09/03, page 384 of 760 As a result, the values in the DMAC are as shown in table 11.10 when the fourth transfer ends, depending on whether the address reload function is on or off. Table 11.10 Values in DMAC after End of Fourth Transfer Items SAR DAR DMATCR Bus right DMAC operation Interrupt Transfer request source flag clearing Address reload on H'04000080 H'003FFFFC H'0000007C Released Stops Not generated Executed Address reload off H'04000090 H'003FFFFC H'0000007C Held Keeps operating Not generated Not executed Notes: 1. An interrupt is generated regardless of whether the address reload function is on or off, if transfers are executed until the value in DMATCR reaches 0 and the IE bit in CHCR has been set to 1. 2. The transfer request source flag is cleared regardless of whether the address reload function is on or off, if transfers are executed until the value in DMATCR reaches 0. 3. Specify burst mode when using the address reload function. This function may not be correctly executed in cycle-steal mode. 4. Set a multiple of four in DMATCR when using the address reload function. This function may not be correctly executed if other values are specified. 11.5.3 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address On) In this example, DMA transfer is performed between the external memory specified by indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC channel 3. Table 11.11 shows the transfer conditions and register settings. In addition, the trigger for the number of transmit FIFO data bytes is set to 1 (TTRG1 = TTRG0 = 1 in SCFCR). Rev. 5.00, 09/03, page 385 of 760 Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Transfer source: External memory Value stored in address H'00400000 Value stored in address H'04500000 Transfer destination: On-chip SCIF TDR2 Number of transfers: 10 Transfer source address: Incremented Transfer destination address: Fixed Transfer request source: SCIF (TXI2) Bus mode: Cycle-steal Transfer unit: Byte No interrupt request generated at end of transfer Channel priority order: 0 > 1 > 2 > 3 DMAOR H'0001 Register SAR3 -- -- DAR3 DMATCR3 CHCR3 Setting H'00400000 H'00450000 H'55 H'04000156 H'0000000A H'00011C01 If the indirect address is on, data stored in the address set in SAR is not used as transfer source data. In the indirect address, after the value stored in the address set in SAR is read, that read value is used as an address again, and the value stored in that address is read and stored in the address set in DAR. In the example shown in table 11.11, when an SCIF transfer request is generated, the DMAC reads the value in address H'00400000 set in SAR3. Since the value H'00450000 is stored in that address, the DMAC reads the value H'00450000. Next, the DMAC uses that read value as an address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value H'55 to address H'04000156 set in DAR3; this completes one indirect address transfer. In the indirect address, when data is read first from the address set in SAR3, the data transfer size is always longword regardless of the settings of the TS0 and TS1 bits that specify the transfer data size. However, whether the transfer source address is fixed, incremented, or decremented is specified by the SM0 and SM1 bits. Therefore, in this example, though the transfer data size is specified as byte, the value in SAR3 is H'00400004 when one transfer ends. Write operations are the same as in normal dual address transfer. Rev. 5.00, 09/03, page 386 of 760 11.6 Usage Notes 1. The DMA channel control registers (CHCR0-CHCR3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longword (32 bits). 2. Before rewriting the RS0-RS3 bits in CHCR0-CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte address, be sure to set the DE bit to 0 in advance). 3. Even if an NMI interrupt is input when the DMAC is not operating, the NMIF bit in DMAOR will be set. 4. Before entering standby mode, the DME bit in DMAOR must be cleared to 0 and the transfers accepted by the DMAC completed. 5. The on-chip peripherals which the DMAC can access are the IrDA, SCIF, A/D converter, D/A converter, and I/O ports. Do not access other peripherals with the DMAC. 6. When starting up the DMAC, set CHCR or DMAOR last. Normal operation is not guaranteed if settings for another register are made last. 7. Even if the maximum number of transfers are performed in the same channel after the DMATCR count reaches 0 and DMA transfer ends normally, write 0 to DMATCR. Otherwise, normal DMA transfer may not be performed. 8. When using the address reload function, specify burst mode as the transfer mode. In cycle-steal mode, normal DMA transfer may not be performed. 9. When using the address reload function, set a multiple of four in DMATCR. Normal operation is not guaranteed if other values are specified. 10. When detecting an external request at the falling edge, keep the external request pin high when setting the DMAC. 11. Do not access the space from H'4000062 to H'400006F, which is not used in the DMAC. Accessing this space may cause malfunctions. 12. The WAIT signal is ignored in the case of a write to external address space in dual address mode with 16-byte transfer, or transfer from an external device with DACK to external address space in signal address mode with 16-byte transfer. 13. DMAC transfers should not be performed in the sleep mode under conditions other than when the clock ratio of I (on-chip clock) to B (bus clock) is 1:1. 14. When the following three conditions are all met, the frequency control register (FRQCR) should not be changed while a DMAC transfer is in progress. * * * Bits IFC2 to IFC0 are changed. STC2 to STC0 in FRQCR are not changed. The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. Rev. 5.00, 09/03, page 387 of 760 Rev. 5.00, 09/03, page 388 of 760 Section 12 Timer (TMU) 12.1 Overview The SH7709S has a three-channel (channels 0 to 2) 32-bit timer unit (TMU). 12.1.1 Features The TMU has the following features: * Each channel is provided with an auto-reload 32-bit down counter. * Channel 2 is provided with an input capture function. * All channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time. * All channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF). * Allows selection between 6 counter input clocks: External clock (TCLK), on-chip RTC output clock (16 kHz), P/4, P/16, P/64, P/256. (P is the internal clock for peripheral modules.) See section 9, On-Chip Oscillation Circuits, for more information on the clock pulse generator. * All channels can operate when the SH7709S is in standby mode: When the RTC output clock is being used as the counter input clock, the SH7709S is still able to count in standby mode. * Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the TCNT so that the entire 32-bit data in the TCNT can be read at once. * The maximum operating frequency of the 32-bit counter is 2 MHz on all channels: Operate the SH7709S so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency. Rev. 5.00, 09/03, page 389 of 760 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. P Prescaler TOCR TCLK RTCCLK Clock controller Ch. 0 TSTR TCR0 Counter controller TCNT0 TCOR0 TUNI0 Interrupt controller Ch. 1 TCR1 Counter controller TCNT1 TCOR1 TUNI1 Interrupt controller Ch. 2 TCR2 Counter controller TCPR2 TCNT2 TCOR2 TUNI2 TICPI2 Interrupt controller Module bus TMU Legend TOCR: Timer output control register TSTR: Timer start register TCR: Timer control register TCNT: 32-bit timer counter TCOR: 32-bit timer constant register TCPR2: 32-bit input capture register Figure 12.1 Block Diagram of TMU Rev. 5.00, 09/03, page 390 of 760 Internal bus Bus interface 12.1.3 Pin Configuration Table 12.1 shows the pin configuration of the TMU. Table 12.1 TMU Pin Channel Clock input/clock output Pin TCLK I/O I/O Description External clock input pin/input capture control input pin/realtime clock (RTC) output pin 12.1.4 Register Configuration Table 12.2 shows the TMU register configuration. Table 12.2 TMU Registers Channel Register Abbreviation TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Initial Value* Address H'00 H'00 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 Undefined H'FFFFFE90 H'FFFFFE92 H'FFFFFE94 H'FFFFFE98 H'FFFFFEA0 H'FFFFFEA4 H'FFFFFEA8 H'FFFFFEB0 H'FFFFFEB4 H'FFFFFEB8 Access Size 8 8 32 32 32 32 16 32 16 32 Common Timer output control register Timer start register 0 Timer constant register 0 Timer counter 0 Timer control register 0 1 Timer constant register 1 Timer counter 1 Timer control register 1 2 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2 H'FFFFFE9C 16 H'FFFFFEAC 32 Note: * Initialized by power-on resets or manual resets. Rev. 5.00, 09/03, page 391 of 760 12.2 12.2.1 TMU Registers Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock. TOCR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 TCOE 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Timer Clock Pin Control (TCOE): Selects use of the timer clock pin (TCLK) as an external clock output pin or input pin for input capture control for the on-chip timer, or as an output pin for the on-chip RTC output clock. Since the TCLK pin is multiplexed as the PTH7 pin, when the pin is used as TCLK, bits PH7MD1 and PH7MD0 in the PHCR register should be set to 00 (the "other function" setting). Bit 0: TCOE 0 1 Description Timer clock pin (TCLK) used as external clock input or input capture control input pin for the on-chip timer (Initial value) Timer clock pin (TCLK) used as output pin for on-chip RTC output clock 12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects whether to run or halt the timer counters (TCNT) for channels 0-2. TSTR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode when the input clock selected for the channel is the on-chip RTC clock (RTCCLK). Only when an external clock (TCLK) or the peripheral clock (P) is used as the input clock, it is initialized in standby mode when the multiplication ratio of PLL circuit 1 is changed or when the MSTP2 bit in STBCR is set to 1. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Rev. 5.00, 09/03, page 392 of 760 Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. Bit 2--Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2). Bit 2: STR2 0 1 Description TCNT2 count halted TCNT2 counts (Initial value) Bit 1--Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1). Bit 1: STR1 0 1 Description TCNT1 count halted TCNT1 counts (Initial value) Bit 0--Counter Start 0 (STR0): Selects whether to run or halt timer counter 0 (TCNT0). Bit 0: STR0 0 1 Description TCNT0 count halted TCNT0 counts (Initial value) 12.2.3 Timer Control Registers (TCR) The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has three TCR registers, one for each channel. The TCR registers are 16-bit readable/writable registers that control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock selection. When the external clock has been selected, they also select its edge. Additionally, TCR2 controls the channel 2 input capture function and the issuance of interrupts during input capture. The TCR registers are initialized to H'0000 by a power-on reset and manual reset, but are not initialized in standby mode and retain their contents. Rev. 5.00, 09/03, page 393 of 760 Channels 0 and 1 TCR Bit Configuration: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 -- 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Channel 2 TCR Bit Configuration: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 ICPE1 0 R/W 14 -- 0 R 6 ICPE0 0 R/W 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 ICPF 0 R/W 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Bits 15 to 10, 9 (except TCR2), 7, and 6 (except TCR2)--Reserved: These bits are always read as 0. The write value should always be 0. Bit 9--Input Capture Interrupt Flag (ICPF): A function of channel 2 only: the flag is set when input capture is requested via the TCLK pin. Bit 9: ICPF 0 1 Description No input capture request has been issued Clearing condition: When 0 is written to ICPF (Initial value) Input capture has been requested via the TCLK pin Setting condition: When input capture is requested via the TCLK pin* Note: * Contents do not change when 1 is written to ICPF. Rev. 5.00, 09/03, page 394 of 760 Bit 8--Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UNF 0 1 Description TCNT has not underflowed Clearing condition: When 0 is written to UNF TCNT has underflowed Setting condition: When TCNT underflows* (Initial value) Note: * Contents do not change when 1 is written to UNF. Bits 7 and 6--Input Capture Control (ICPE1, ICPE0): A function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. When using this input capture function it is necessary to set the TCLK pin to input mode with the TCOE bit in the TOCR register. Additionally, use the CKEG bit to designate use of either the rising or falling edge of the TCLK pin to set the value in TCNT2 in the input capture register (TCPR2). Bit 7: ICPE1 0 1 Bit 6: ICPE0 0 1 0 1 Description Input capture function is not used Reserved (Setting prohibited) Input capture function is used. Interrupt due to ICPF (TICPI2) is not enabled Input capture function is used. Interrupt due to ICPF (TICPI2) is enabled (Initial value) Bit 5--Underflow Interrupt Control (UNIE): Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1. Bit 5: UNIE 0 1 Description Interrupt due to UNF (TUNI) is not enabled Interrupt due to UNF (TUNI) is enabled (Initial value) Rev. 5.00, 09/03, page 395 of 760 Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): Select the external clock edge when the external clock is selected, or when the input capture function is used. Bit 4: CKEG1 0 1 Bit 3: CKEG0 0 1 X Description Count/capture register set on rising edge Count/capture register set on falling edge Count/capture register set on both rising and falling edge (Initial value) Note: X means 0, 1, or `Don't care'. Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2 to TPSC0): Select the TCNT count clock. Bit 2: TPSC2 0 Bit 1: TPSC1 0 1 1 0 Bit 0: TPSC0 0 1 0 1 0 1 1 0 1 Description Internal clock: count on P/4 Internal clock: count on P/16 Internal clock: count on P/64 Internal clock: count on P/256 Internal clock: count on clock output of on-chip RTC (RTC CLK) Count on TCLK pin input Reserved (Setting prohibited) Reserved (Setting prohibited) (Initial value) Rev. 5.00, 09/03, page 396 of 760 12.2.4 Timer Constant Registers (TCOR) The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in TCNT when a TCNT count-down results in an under flow. TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 1 R/W 23 1 R/W 15 1 R/W 7 1 R/W 30 1 R/W 22 1 R/W 14 1 R/W 6 1 R/W 29 1 R/W 21 1 R/W 13 1 R/W 5 1 R/W 28 1 R/W 20 1 R/W 12 1 R/W 4 1 R/W 27 1 R/W 19 1 R/W 11 1 R/W 3 1 R/W 26 1 R/W 18 1 R/W 10 1 R/W 2 1 R/W 25 1 R/W 17 1 R/W 9 1 R/W 1 1 R/W 24 1 R/W 16 1 R/W 8 1 R/W 0 1 R/W 12.2.5 Timer Counters (TCNT) The timer counters are 32-bit readable/writable registers. The TMU has three timer counters, one for each channel. TCNT counts down upon input of a clock. The clock input is selected using the TPSC2-TPSC0 bits in the timer control register (TCR). When a TCNT count-down results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the count-down continues from that value. Rev. 5.00, 09/03, page 397 of 760 Because the internal bus for the SH7709S on-chip peripheral modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. To correct the discrepancy, a buffer register is connected to TCNT so that the upper and lower halves are not read separately. The entire 32-bit data in TCNT can thus be read at once. TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 1 R/W 23 1 R/W 15 1 R/W 7 1 R/W 30 1 R/W 22 1 R/W 14 1 R/W 6 1 R/W 29 1 R/W 21 1 R/W 13 1 R/W 5 1 R/W 28 1 R/W 20 1 R/W 12 1 R/W 4 1 R/W 27 1 R/W 19 1 R/W 11 1 R/W 3 1 R/W 26 1 R/W 18 1 R/W 10 1 R/W 2 1 R/W 25 1 R/W 17 1 R/W 9 1 R/W 1 1 R/W 24 1 R/W 16 1 R/W 8 1 R/W 0 1 R/W Rev. 5.00, 09/03, page 398 of 760 12.2.6 Input Capture Register (TCPR2) Input capture register 2 (TCPR2) is a read-only 32-bit register provided only in timer 2. Control of TCPR2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE0 and CKEG1/CKEG0) in TCR2. When a TCPR2 setting indication due to the TCLK pin occurs, the value of TCNT2 is copied into TCPR2. TCNT2 is not initialized by a power-on reset or manual reset, but is not initialized, and retains its contents, or in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R 23 -- R 15 -- R 7 -- R 30 -- R 22 -- R 14 -- R 6 -- R 29 -- R 21 -- R 13 -- R 5 -- R 28 -- R 20 -- R 12 -- R 4 -- R 27 -- R 19 -- R 11 -- R 3 -- R 26 -- R 18 -- R 10 -- R 2 -- R 25 -- R 17 -- R 9 -- R 1 -- R 24 -- R 16 -- R 8 -- R 0 -- R Rev. 5.00, 09/03, page 399 of 760 12.3 TMU Operation Each of three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). TCNT counts down. The auto-reload function enables cycle counting and counting by external events. Channel 2 has an input capture function. 12.3.1 General Operation When the STR0-STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer counter (TCNT) starts counting. When a TCNT underflows, the UNF flag of the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the down-count operation is continued. The count operation is set as follows (figure 12.2): 1. Select the counter clock with the TPSC2-TPSC0 bits in the timer control register (TCR). If the external clock is selected, set the TCLK pin to input mode with the TOCE bit in TOCR, and select its edge with the CKEG1 and CKEG0 bits in TCR. 2. Use the UNIE bit in TCR to set whether to generate an interrupt when TCNT underflows. 3. When using the input capture function, set the ICPE bits in TCR, including the choice of whether or not to use the interrupt function (channel 2 only). 4. Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1). 5. Set the initial value in the timer counter (TCNT). 6. Set the STR bit in the timer start register (TSTR) to 1 to start operation. Rev. 5.00, 09/03, page 400 of 760 Select operation Select counter clock (1) Set underflow interrupt generation (2) When using input capture function Set interrupt generation (3) Set timer constant register Initialize timer counter (4) (5) Start counting (6) Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 12.2 Setting the Count Operation Rev. 5.00, 09/03, page 401 of 760 Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR H'00000000 STR0-STR2 UNF Time Figure 12.3 Auto-Reload Count Operation TCNT Count Timing: * Internal Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select whether peripheral module clock P or one of the four internal clocks created by dividing it is used (P/4, P/16, P/64, P/256). Figure 12.4 shows the timing. P Internal clock TCNT input clock TCNT N+1 N N-1 Figure 12.4 Count Timing when Operating on Internal Clock Rev. 5.00, 09/03, page 402 of 760 * External Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rising, falling, or both edges may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. A shorter pulse width will result in accurate operation. Figure 12.5 shows the timing for both-edge detection. P External clock input pin (TCLK) TCNT input clock TCNT N+1 N N-1 Figure 12.5 Count Timing when Operating on External Clock (Both Edges Detected) * On-Chip RTC Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select the on-chip RTC clock as the timer clock. Figure 12.6 shows the timing. RTC output clock TCNT input clock TCNT N + 1 N N-1 Figure 12.6 Count Timing when Operating on On-Chip RTC Clock 12.3.2 Input Capture Function Channel 2 has an input capture function (figure 12.7). When using the input capture function, set the TCLK pin to input mode with the TCOE bit in the timer output control register (TOCR) and set the timer operation clock to internal clock or on-chip RTC clock with the TPCS2-TPCS0 bits in the timer control register (TCR2). Also, designate use of the input capture function and whether to generate interrupts on input capture with the IPCE1-IPCE0 bits in TCR2, and designate the use of either the rising or falling edge of the TCLK pin to set the timer counter (TCNT2) value into the input capture register (TCPR2) with the CKEG1-CKEG0 bits in TCR2. The input capture function cannot be used in standby mode. Rev. 5.00, 09/03, page 403 of 760 TCNT value TCOR TCOR value set to TCNT during underflow H'00000000 TCLK Time TCPR2 Set TCNT value ICPI Figure 12.7 Operation Timing when Using Input Capture Function (Using TCLK Rising Edge) 12.4 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 12.4.1 Status Flag Setting Timing UNF is set to 1 when the TCNT underflows. Figure 12.8 shows the timing. P TCNT Underflow signal UNF TUNI H'00000000 TCOR value Figure 12.8 UNF Setting Timing Rev. 5.00, 09/03, page 404 of 760 12.4.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. TCR write cycle T1 P Peripheral address bus UNF, ICPF TCR address T2 T3 Figure 12.9 Status Flag Clearing Timing 12.4.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, an interrupt is requested. Codes are set in the interrupt event registers (INTEVT, INTEVT2) for these interrupts and interrupt handling occurs according to the codes. The relative priorities of channels can be changed using the interrupt controller (see section 4, Exception Handling, and section 6, Interrupt Controller (INTC)). Table 12.3 lists TMU interrupt sources. Table 12.3 TMU Interrupt Sources Channel 0 1 2 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Low Priority High Rev. 5.00, 09/03, page 405 of 760 12.5 12.5.1 Usage Notes Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2-STR0) in the timer start register (TSTR) to halt timer counting. 12.5.2 Reading Registers Synchronization processing is performed for timer counting during register reads. When timer counting and register read processing are performed simultaneously, the register value before TCNT counting down (with synchronization processing) is read. Rev. 5.00, 09/03, page 406 of 760 Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. 13.1.1 Features * Clock and calendar functions (BCD display): Seconds, minutes, hours, date, day of the week, month, and year * 1-Hz to 64-Hz timer (binary display) * Start/stop function * 30-second adjust function * Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, and month can be used as conditions for the alarm interrupt * Cyclic interrupts: The interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: A carry interrupt indicates when a carry occurs during a counter read * Automatic leap year correction Rev. 5.00, 09/03, page 407 of 760 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the RTC. Externally connected circuit EXTAL2 Oscillator circuit XTAL2 32.768 kHz Prescaler (/ 2) RTCCLK 16.384 kHz 128 Hz 30second Reset ADJ RSECCNT RMINCNT RHRCNT RWKCNT Prescaler (/ 128) RDAYCNT RMONCNT RYRCNT ATI PRI RSECAR RMINAR CUI Carry detection circuit RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 Legend R64CNT: RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: 64 Hz counter Second counter Minute counter Hour counter Day-of-week counter Day counter Month counter Year counter RSECAR: RMINAR: RHRAR: RWKAR: RDAYAR: RMONAR: RCR1: RCR2: Second alarm register Minute alarm register Hour alarm register Day-of-week alarm register Day alarm register Month alarm register RTC control register 1 RTC control register 2 Figure 13.1 Block Diagram of RTC Rev. 5.00, 09/03, page 408 of 760 Module bus Interrupt control circuit Comparator RTC Internal bus R64CNT Bus interface 13.1.3 Pin Configuration Table 13.1 shows the RTC pin configuration. Table 13.1 RTC Pins Pin RTC oscillator crystal pin RTC oscillator crystal pin Clock input/clock output Signal Name EXTAL2 XTAL2 TCLK I/O I O I/O Description Connects crystal to RTC oscillator* 2 Connects crystal to RTC oscillator* External clock input pin/input capture control input pin/realtime clock (RTC) output pin (shared by TMU) 1 Dedicated power-supply pin for RTC* Dedicated GND pin for RTC* 1 2 Dedicated power-supply pin for RTC Dedicated GND pin for RTC Vcc-RTC Vss-RTC -- -- Notes: 1. Except in hardware standby mode, power must be supplied to all power supply pins, including these, even when only the RTC is used (including standby mode). 2. When the RTC is not used, pull EXTAL2 up (to Vcc) and make no connection for XTAL2. Rev. 5.00, 09/03, page 409 of 760 13.1.4 RTC Register Configuration Table 13.2 shows the RTC register configuration. Table 13.2 RTC Registers Name 64-Hz counter Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 Abbreviation R/W R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RDAYAR RMONAR RCR1 RCR2 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* H'00 H'09 Address H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Day of week alarm register RWKAR Note: * Only the ENB bits of each register are initialized. Rev. 5.00, 09/03, page 410 of 760 13.2 13.2.1 RTC Registers 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the states of the RTC divider circuit, RTC prescaler, and R64CNT between 64 Hz and 1 Hz. R64CNT is initialized to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 to 1. R64CNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 is always read as 0. Bit: Initial value: R/W: 7 -- 0 R 6 1Hz -- R 5 2Hz -- R 4 4Hz -- R 3 8Hz -- R 2 16Hz -- R 1 32Hz -- R 0 64Hz -- R 13.2.2 Second Counter (RSECCNT) The second counter (RSECCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded second section of the RTC. The count operation is performed by a carry for each second of the 64-Hz counter. The range that can be set is 00-59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 -- R/W 1 -- R/W 0 -- R/W 1 second Rev. 5.00, 09/03, page 411 of 760 13.2.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range that can be set is 00-59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 -- R/W 1 -- R/W 0 -- R/W 1 minute 13.2.4 Hour Counter (RHRCNT) The hour counter (RHRCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the minute counter. The range that can be set is 00-23 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2 or using a carry flag as shown in figure 13.2. RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- R/W 4 -- R/W 3 -- R/W 2 1 hour -- R/W -- R/W -- R/W 1 0 10 hours Rev. 5.00, 09/03, page 412 of 760 13.2.5 Day of Week Counter (RWKCNT) The day of week counter (RWKCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range that can be set is 0-6 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0 Days of the week are coded as shown in table 13.3. Table 13.3 Day-of-Week Codes (RWKCNT) Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6 Rev. 5.00, 09/03, page 413 of 760 13.2.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range that can be set is 01-31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode. The RDAYCNT range that can be set changes with each month and in leap years. Please confirm the correct setting. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0 13.2.7 Month Counter (RMONCNT) The month counter (RMONCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded month section of the RTC. The count operation is performed by a carry for each month of the date counter. The range that can be set is 00-12 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0 Rev. 5.00, 09/03, page 414 of 760 13.2.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range that can be set is 00-99 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode. Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. The year counter value: 00 is included in leap years. Bit: Initial value: R/W: 7 -- R/W 6 10 years -- R/W -- R/W -- R/W -- R/W -- R/W 5 4 3 2 1 year -- R/W -- R/W 1 0 13.2.9 Second Alarm Register (RSECAR) The second alarm register (RSECAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-59 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 -- R/W 1 -- R/W 0 -- R/W 1 second Rev. 5.00, 09/03, page 415 of 760 13.2.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-59 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 minute -- R/W -- R/W -- R/W 1 0 13.2.11 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded hour section counter RHRCNT of the RTC. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-23 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The remaining RHRAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- R/W 4 -- R/W 3 -- R/W 2 1 hour -- R/W -- R/W -- R/W 1 0 10 hours Rev. 5.00, 09/03, page 416 of 760 13.2.12 Day of Week Alarm Register (RWKAR) The day of week alarm register (RWKAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 0-6 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The remaining RWKAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0 Days of the week are coded as shown in table 13.4. Table 13.4 Day-of-Week Codes (RWKAR) Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6 Rev. 5.00, 09/03, page 417 of 760 13.2.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 01-31 (decimal) + ENB bit. Errant operation will result if any other value is set. The RDAYCNT range that can be set changes with some months and in leap years. Please confirm the correct setting. The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0 13.2.14 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 01-12 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The remaining RMONAR fields are not initialized and retain their contents by a manual reset, or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0 Rev. 5.00, 09/03, page 418 of 760 13.2.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit readable/writable register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset or a manual reset. In a manual reset, all bits are initialized to H'00 except for the CF flag, which is undefined. When using the CF flag, it must be initialized beforehand. This register is not initialized in standby mode. Bit: Initial value: R/W: 7 CF 0 R/W 6 -- 0 R 5 -- 0 R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- 0 R 1 -- 0 R 0 AF 0 R/W Bit 7--Carry Flag (CF): Status flag that indicates that a carry has occurred. Setting CF to 1 indicates reading of a counter register value has occurred when (1) the second counter is carried or (2) the 64-Hz counter is carried. A count register value read at this time cannot be guaranteed; another read is required. Bit 7: CF 0 1 Description No count up of R64CNT or RSECCNT Clearing condition: When 0 is written to CF Count up of R64CNT or RSECCNT Setting condition: When 1 is written to CF (Initial value) Bits 6, 5, 2, and 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--Carry Interrupt Enable Flag (CIE): When the carry flag (CF) is set to 1, the CIE bit enables interrupts. Bit 4: CIE 0 1 Description A carry interrupt is not generated when the CF flag is set to 1 A carry interrupt is generated when the CF flag is set to 1 (Initial value) Rev. 5.00, 09/03, page 419 of 760 Bit 3--Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. Bit 3: AIE 0 1 Description An alarm interrupt is not generated when the AF flag is set to 1 (Initial value) An alarm interrupt is generated when the AF flag is set to 1 Bit 0--Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to 0 when 0 is written, but holds its previous value when 1 is written. Bit 0: AF 0 1 Description Clock/calendar and alarm register have not matched since last reset to 0 Clearing condition: When 0 is written to AF (Initial value) Setting condition: Clock/calendar and alarm register have matched (only registers with ENB set)* Note: * Contents do not change when 1 is written to AF. 13.2.16 RTC Control Register 2 (RCR2) The RTC control register 2 (RCR2) is an 8-bit readable/writable register for periodic interrupt control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a manual reset. It is not initialized, and retains its contents, in standby mode. Bit: Initial value: R/W: 7 PEF 0 R/W 6 PES2 0 R/W 5 PES1 0 R/W 4 PES0 0 R/W 3 RTCEN 1 R/W 2 ADJ 0 R/W 1 RESET 0 R/W 0 START 1 R/W Bit 7--Periodic Interrupt Flag (PEF): Indicates interrupt generation with the period designated by the PES bits. When set to 1, PEF generates periodic interrupts. Bit 7: PEF 0 1 Description Interrupts not generated with the period designated by the PES bits Clearing condition: When 0 is written to PEF (Initial value) Interrupts generated with the period designated by the PES bits Setting condition: When 1 is written to PEF Rev. 5.00, 09/03, page 420 of 760 Bits 6 to 4--Periodic Interrupt Flags (PES2-PES0): Specify the periodic interrupt. Bit 6: PES2 0 Bit 5: PES1 0 Bit 4: PES0 0 1 1 0 1 1 0 0 1 1 0 1 Description No periodic interrupts generated (Initial value) Periodic interrupt generated every 1/256 second Periodic interrupt generated every 1/64 second Periodic interrupt generated every 1/16 second Periodic interrupt generated every 1/4 second Periodic interrupt generated every 1/2 second Periodic interrupt generated every 1 second Periodic interrupt generated every 2 seconds Bit 3--RTCEN: Controls the operation of the crystal oscillator for the RTC. Bit 3: RTCEN 0 1 Description Crystal oscillator for RTC is halted Crystal oscillator for RTC runs (Initial value) Bit 2--30 Second Adjustment (ADJ): When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit, RTC prescaler, and R64CNT will be simultaneously reset. This bit is always read as 0. The maximum duration between when the ADJ bit is set to 1 and when the new setting is reflected in the readout value from the seconds counter (RSECCNT) is approximately 91.6 s (when a 32.768 kHz quartz oscillator is connected to the EXTAL2 pin). Bit 2: ADJ 0 1 (Write) Description Runs normally 30-second adjustment (Initial value) Bit 1--Reset (RESET): When 1 is written, initializes the divider circuit (RTC prescaler and R64CNT). This bit is always read as 0. Bit 1: RESET 0 1 (Write) Description Runs normally Divider circuit is reset (Initial value) Rev. 5.00, 09/03, page 421 of 760 Bit 0--Start Bit (START): Halts and restarts the counter (clock). Bit 0: START 0 1 Description Second/minute/hour/day/week/month/year counter halts Second/minute/hour/day/week/month/year counter runs normally (Initial value) Note: The 64-Hz counter always runs unless stopped with the RTCEN bit. 13.3 13.3.1 RTC Operation Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 13.3.2 Setting the Time Figure 13.2 shows how to set the time when the clock is stopped. This works when the entire calendar or clock is to be set. Programming can be easily performed. To reset the divider circuit (RTC prescaler and R64CNT) and set the counter Stop clock, reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Start clock Write 1 to START in the RCR2 register Figure 13.2 Setting the Time Rev. 5.00, 09/03, page 422 of 760 13.3.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts; part (b) in figure 13.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. a. To read the time without using interrupts Disable the carry interrupt Clear the carry flag Read counter register Yes Carry flag = 1? No Read RCR1 and check CF Clear CIE in RCR1 to 0 Write 0 to CF in RCR1 Note: Set AF to 1 so that alarm flag is not cleared. b. To use interrupts Enable the carry interrupt Clear the carry flag Read counter register Yes Interrupt generated? No Disable the carry interrupt Write 1 to CIE in RCR1, and write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. Write 0 to CIE in RCR1 Figure 13.3 Reading the Time Rev. 5.00, 09/03, page 423 of 760 13.3.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) to 1 in the register to which the alarm applies, and then set the alarm time in the lower bits. Clear the ENB bit to 0 in registers to which the alarm does not apply. When the clock and alarm times match, 1 is set in the AF bit (bit 0) in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is placed in the AIE bit (bit 3) in RCR1, an interrupt is generated when an alarm occurs. Clock running Set whether to use alarm interrupt Disable interrupts for preventing error interrupts (clear the AIE bit in RCR1 to 0). Then write 1 to the AIE bit in RCR1. Set alarm time Always reset, since the flag may have been set while the alarm time was being set (clear the AF bit in RCR1 to 0). Clear alarm flag Monitor alarm time (wait for interrupt or check alarm flag) Figure 13.4 Using the Alarm Function Rev. 5.00, 09/03, page 424 of 760 13.3.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 13.5, and the RTC crystal oscillator circuit in figure 13.5. Table 13.5 Recommended Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10 to 22 pF Cout 10 to 22 pF SH7709S EXTAL2 Rf RD XTAL2 XTAL Cin Cout Notes: 1. Select either the Cin or Cout side for the frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a ground plane. 4. The crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. Figure 13.5 Example of Crystal Oscillator Circuit Connection Rev. 5.00, 09/03, page 425 of 760 13.4 13.4.1 Usage Notes Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 13.6. A periodic interrupt can be generated periodically at the interval set by the periodic interrupt enable flag (PES) in RTC control register 2 (RCR2). When the time set by the periodic interrupt enable flag (PES) has elapsed, the periodic interrupt flag (PEF) is set to 1. The periodic interrupt flag (PEF) is cleared to 0 upon periodic interrupt generation when the periodic interrupt enable flag (PES) is set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. Set PES, and clear PEF to 0, in RCR2 Set PES, clear PEF Elapse of time set by PES Clear PEF Clear PEF to 0 Figure 13.6 Using Periodic Interrupt Function 13.4.3 Precautions when Using RTC Module Standby Before switching the RTC to module standby, access at least one among the registers RTC, SCI, and TMU. Rev. 5.00, 09/03, page 426 of 760 Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7709S has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communication feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards. See section 15, Smart Card Interface, for more information. 14.1.1 Features Selection of asynchronous or synchronous as the serial communication mode. * Asynchronous mode: Serial data communication is synchronized by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. It can also communicate with two or more other processors using the multiprocessor communication function. There are 12 selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: By reading the RxD level directly from the SC port data register (SCPDR) when a framing error occurs * Synchronous mode: Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. Data length: 8 bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates Rev. 5.00, 09/03, page 427 of 760 * Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. * When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus SCRDR SCTDR RxD SCRSR SCTSR TxD SCPCR SCPDR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR Baud rate generator P P/4 P/16 P/64 Parity generation Parity check Clock External clock TEI TXI RXI ERI SCK SCI Legend SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCSCR: SCSSR: SCBRR: SCPDR: SCPCR: Serial control register Serial status register Bit rate register SC port data register SC port control register Figure 14.1 Block Diagram of SCI Rev. 5.00, 09/03, page 428 of 760 Figures 14.2, 14.3, and 14.4 show block diagrams of the SCI I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR). Reset R D SCP1MD0 Q C PCRW Reset R Q D SCP1MD1 C PCRW Reset SCPT[1]/SCK0 R Q D SCP1DT1 C PDRW Output enable Serial clock output Clock input enable Internal data bus SCI PDRR* Serial clock input Legend PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1 (see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)). Figure 14.2 SCPT[1]/SCK0 Pin Rev. 5.00, 09/03, page 429 of 760 Reset R D SCP0MD0 Q C PCRW Reset R Q D SCP0MD1 C PCRW Reset SCPT[0]/TxD0 R Q D SCP0DT1 C PDRW Output enable Serial transmission output Internal data bus SCI Legend PCRW: SCPCR write PDRW: SCPDR write Figure 14.3 SCPT[0]/TxD0 Pin Rev. 5.00, 09/03, page 430 of 760 SCI SCPT[0]/RxD0 Serial receive data Internal data bus PDRR* Legend PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 14.4 SCPT[0]/RxD0 Pin 14.1.3 Pin Configuration The SCI has the serial pins summarized in table 14.1. Table 14.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 I/O I/O Input Output Function Clock I/O Receive data input Transmit data output Note: These pins are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR and the C/A bit in SCSMR. Break state transmission and detection can be performed by means of the SCI's SCSPTR register. Rev. 5.00, 09/03, page 431 of 760 14.1.4 Register Configuration Table 14.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 14.2 SCI Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register SC port data register SC port control register Abbreviation SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCPDR SCPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'A888 Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A Access size 8 8 8 8 8 8 H'04000136 8 2 (H'A4000136)* H'04000116 16 2 (H'A4000116)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. The only value that can be written is 0 to clear the flags. 2. When address translation by the MMU does not apply, the address in parentheses should be used. 14.2 14.2.1 Register Descriptions Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Rev. 5.00, 09/03, page 432 of 760 14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 14.2.3 Transmit Shift Register (SCTSR) The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one-byte data, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1, however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write to SCTSR directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Rev. 5.00, 09/03, page 433 of 760 14.2.4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in SCTDR during serial transmission from SCTSR. The CPU can always read and write to SCTDR. SCTDR is initialized to H'FF by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W 14.2.5 Serial Mode Register (SCSMR) The serial mode register (SCSMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'00 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Communication Mode (C/A): Selects whether the SCI operates in asynchronous or A synchronous mode. Bit 7: C/A A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Rev. 5.00, 09/03, page 434 of 760 Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not transmitted. Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked* (Initial value) Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. E The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. Bit 4: O/E E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 5.00, 09/03, page 435 of 760 Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 1 Description One stop bit* 2 Two stop bits* 1 (Initial value) Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1-bits are added at the end of each transmitted character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the onchip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64 can be set according to the setting of the CKS1 and CKS0 bits. For further information on the clock source, bit rate register settings, and baud rate, see section 14.2.9, Bit Rate Register (SCBRR). Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Note: P: Peripheral clock Description P P/4 P/16 P/64 (Initial value) Rev. 5.00, 09/03, page 436 of 760 14.2.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SCSSR) is set to 1 due to transfer of serial transmit data from SCTDR to SCTSR. Bit 7: TIE 0 1 Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled (Initial value) Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set to 1 due to transfer of serial receive data from SCRSR to SCRDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled* (Initial value) Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. Rev. 5.00, 09/03, page 437 of 760 Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE 0 1 Description Transmitter disabled* 2 Transmitter enabled* 1 (Initial value) Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1. 2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR. Select the transmit format in SCSMR before setting TE to 1. Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4: RE 0 1 Description Receiver disabled* 2 Receiver enabled* 1 (Initial value) Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SCSMR before setting RE to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] (1) MPE is cleared to 0 when MPIE is cleared to 0. 1 (2) The multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled* Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SCSSR) are disabled until data with a multiprocessor bit of 1 is received. Note: * The SCI does not transfer receive data from SCRSR to SCRDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SCSSR). When it receives data that includes MPB = 1, the SCSSR's MPB flag is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be set. Rev. 5.00, 09/03, page 438 of 760 Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted. Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled * (Initial value) Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0, or by clearing the TEIE bit to 0. Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source, see table 14.10 in section 14.3, Operation. Bit 1: CKE1 0 Bit 0: CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) (Initial value) Internal clock, SCK pin used for synchronous clock output (Initial value) 1 Internal clock, SCK pin used for clock output* Internal clock, SCK pin used for synchronous clock output 2 External clock, SCK pin used for clock input* External clock, SCK pin used for synchronous clock input 2 External clock, SCK pin used for clock input* External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is the same as the bit rate. 2. The input clock frequency is 16 times the bit rate. Rev. 5.00, 09/03, page 439 of 760 14.2.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SCSSR is initialized to H'84 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * The only value that can be written is 0 to clear the flag. Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from SCTDR into SCTSR and new serial transmit data can be written in SCTDR. Bit 7: TDRE 0 Description SCTDR contains valid transmit data [Clearing condition] TDRE is cleared to 0 when software reads TDRE after it has been set to 1. 1 SCTDR does not contain valid transmit data [Setting conditions] (1) TDRE is set to 1 when the chip is reset or enters standby mode. (2) The TE bit in the serial control register (SCSCR) is cleared to 0. (3) SCTDR contents are loaded into SCTSR, so new data can be written in SCTDR. (Initial value) Rev. 5.00, 09/03, page 440 of 760 Bit 6--Receive Data Register Full (RDRF): Indicates that SCRDR contains received data. Bit 6: RDRF 0 Description SCRDR does not contain valid receive data [Clearing conditions] (1) RDRF is cleared to 0 when the chip is reset or enters standby mode. (2) Software reads RDRF after it has been set to 1, then writes 0 in RDRF. 1 SCRDR contains valid receive data [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from SCRSR to SCRDR. Note: SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost. (Initial value) Bit 5--Overrun Error (ORER): Indicates that data reception aborted due to an overrun error. Bit 5: ORER 0 Description 1 Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) ORER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads ORER after it has been set to 1, then writes 0 to ORER. 2 A receive overrun error occurred* [Setting condition] ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1. Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. SCRDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is also disabled. 1 Rev. 5.00, 09/03, page 441 of 760 Bit 4--Framing Error (FER): Indicates that data reception aborted due to a framing error in asynchronous mode. Bit 4: FER 0 Description 1 Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) FER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads FER after it has been set to 1, then writes 0 to FER. 1 A receive framing error occurred [Setting condition] FER is set to 1 if the stop bit at the end of receive data is checked and found to 2 be 0.* Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. 2. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 3--Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity error in asynchronous mode. Bit 3: PER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] (1) PER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads PER after it has been set to 1, then writes 0 to PER. 1 A receive parity error occurred* [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SCSMR). Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. 2. When a parity error occurs, the SCI transfers the receive data into SCRDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In synchronous mode, serial transmitting is also disabled. 2 1 (Initial value) Rev. 5.00, 09/03, page 442 of 760 Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written to. Bit 2: TEND 0 Description Transmission is in progress [Clearing condition] TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 to TDRE. 1 End of transmission [Setting conditions] (1) TEND is set to 1 when the chip is reset or enters standby mode. (2) When TE is cleared to 0 in the serial control register (SCSCR). (3) If TDRE is 1 when the last bit of a one-byte serial character is transmitted. (Initial value) Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a read-only bit and cannot be written to. Bit 1: MPB 0 1 Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 (Initial value) Note: * If RE is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) Rev. 5.00, 09/03, page 443 of 760 14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR) The SC port control register (SCPCR) and SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins. SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to the TxD pin, and input data to be read from the RxD pin, and to control serial transmission/reception breaks. It is also possible to read data on the SCK pin, and write output data. SCPCR Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SCPDR Bit: Initial value: R/W: 7 0 R 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT SCI pin I/O and data control are performed by bits 3-0 of SCPCR and bits 1 and 0 of SCPDR. SCPCR Bits 3 and 2--Serial Clock Port I/O (SCP1MD1, SCP1MD0): Specify serial port SCK pin I/O. When the SCK pin is actually used as a port I/O pin, clear the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR to 0. Bit 3: SCP1MD1 0 0 1 1 Bit 2: SCP1MD0 0 1 0 1 Description SCP1DT bit value is not output to SCK pin SCP1DT bit value is output to SCK pin SCK pin value is read from SCP1DT bit (Initial values: 1 and 0) Rev. 5.00, 09/03, page 444 of 760 SCPDR Bit 1--Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or output is specified by the SCP1MD1 and SCP1MD0 bits. In output mode, the value of the SCP1DT bit is output to the SCK pin. Bit 1: SCP1DT 0 1 Description I/O data is low I/O data is high (Initial value) SCPCR Bits 1 and 0--Serial Port Break I/O (SCP0MD1, SCP0MD0): Specify the serial port TxD pin output condition. When the TxD pin is actually used as a port output pin and outputs the value set with the SCP0DT bit, clear the TE bit in SCSCR to 0. Bit 1: SCP0MD1 0 0 Bit 0: SCP0MD0 0 1 Description SCP0DT bit value is not output to TxD pin SCP0DT bit value is output to TxD pin (Initial value) SCPDR Bit 0--Serial Port Break Data (SCP0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SCP0MD1 and SCP0MD0 bits. When the TxD pin is set to output mode, the value of the SCP0DT bit is output to the TxD pin. The RxD pin value is read from the SCP0DT bit regardless of the values of the SCP0MD1 and SCP0MD0 bits, if RE in SCSCR is set to 1. The initial value of this bit after a power-on reset is undefined. Bit 0: SCP0DT 0 1 Description I/O data is low I/O data is high (Initial value) Block diagrams of the SCI I/O port pins are shown in figures 14.2, 14.3, and 14.4. Rev. 5.00, 09/03, page 445 of 760 14.2.9 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The SCBRR setting is calculated as follows: Asynchronous mode: N = P 64 x 22n - 1 x B P 8 x 22n - 1 x B x 106 - 1 Synchronous mode: N = B: N: P: n: x 106 - 1 Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14.3.) Table 14.3 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: The bit rate error in asynchronous is given by the following formula: P x 106 Error (%) = ( ) x 100 (N + 1) x B x 64 x 22n - 1 Rev. 5.00, 09/03, page 446 of 760 Table 14.4 lists examples of SCBRR settings in asynchronous mode, and table 14.5 lists examples of SCBRR settings in synchronous mode. Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode P (MHz) 2 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) n % -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 P (MHz) 3 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 3.6864 Error (%) n % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 Rev. 5.00, 09/03, page 447 of 760 P (MHz) 4.9152 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) n % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) n % -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 P (MHz) 6.144 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) n % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 7.3728 Error (%) n % -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 Rev. 5.00, 09/03, page 448 of 760 P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 2 2 1 1 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 -1.70 0 -1.70 0 P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (%) % 0.31 0.46 0.46 0.46 0.46 n 3 3 2 1 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) % 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 -0.44 3 3 2 2 1 1 0 0 0 0 -0.08 2 -0.08 1 -0.08 0 -0.61 0 -1.03 0 1.55 0 -1.70 0 -2.34 0 Rev. 5.00, 09/03, page 449 of 760 Table 14.5 Bit Rates and SCBRR Settings in Synchronous Mode P (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 4 n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- Notes: Settings with an error of 1% or less are recommended. Blank: No setting possible --: Setting possible, but error occurs *: Continuous transmit/receive operation not possible Rev. 5.00, 09/03, page 450 of 760 Table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 14.7 and 14.8 list the maximum rates for external clock input. Table 14.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 5.00, 09/03, page 451 of 760 Table 14.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 14.8 Maximum Bit Rates with External Clock Input (Synchronous Mode) P (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev. 5.00, 09/03, page 452 of 760 14.3 14.3.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous/synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as shown in table 14.9. The SCI clock source is selected by the combination of the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 14.10. Asynchronous Mode: * Data length is selectable: 7 or 8 bits. * Parity and multiprocessor bits are selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER) and breaks. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: * The transmission/reception format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 5.00, 09/03, page 453 of 760 Table 14.9 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings Bit 7 Bit 6 C/A CHR A 0 0 Bit 5 PE 0 1 1 0 1 0 1 1 * * * * * * * 1 Bit 2 MP 0 Bit 3 STOP 0 1 0 1 0 1 0 1 0 1 0 1 * Synchronous 8-bit Not set Asynchronous (multiprocessor format) 8-bit 7-bit Not set Set Set 7-bit Not set Set Mode Asynchronous SCI Communication Format Data Length 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: Asterisks (*) indicate don't care bits. Table 14.10 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR Bit 7 C/A A 0 SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Outputs the synchronous clock Inputs the synchronous clock Rev. 5.00, 09/03, page 454 of 760 14.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 14.5 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first; starting from the lowerest bit), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idle (mark) state 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit 1 Serial data 0 Start bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 One unit of communication data (character or frame) Figure 14.5 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Rev. 5.00, 09/03, page 455 of 760 Transmit/Receive Formats: Table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 14.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 START START START START START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data Notes: -- : START: STOP: P: MPB: Don't care bits Start bit Stop bit Parity bit Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 14.10). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. Rev. 5.00, 09/03, page 456 of 760 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.6 Output Clock and Serial Data Timing (Asynchronous Mode) Transmitting and Receiving Data (SCI Initialization (Asynchronous Mode)): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 14.7 shows a sample flowchart for initializing the SCI. The procedure for initializing the SCI is: 1. Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCSCR. 2. Select the communication format in the serial mode register (SCSMR). 3. Write the value corresponding to the bit rate in the bit rate register (SCBRR) (not necessary if an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial state is the mark state when transmitting, or the idle state (waiting for a start bit) when receiving. Rev. 5.00, 09/03, page 457 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select communication format in SCSMR Set value in SCBRR Wait Has a 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) No (1) (2) (3) End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.7 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 14.8 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For SCPCR and SCPDR settings, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR). Rev. 5.00, 09/03, page 458 of 760 Start of transmission Read TDRE bit in SCSSR (1) No TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 (2) All data transmitted? Yes Read TEND bit in SCSSR No TEND = 1? Yes Break output? Yes Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 End of transmission (3) No No Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.8 Sample Flowchart for Transmitting Serial Data Rev. 5.00, 09/03, page 459 of 760 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1-bits (stop bits) are output. e. Marking: Output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SCSSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCSCR is set to 1, a transmit-end interrupt (TEI) is requested. Rev. 5.00, 09/03, page 460 of 760 Figure 14.9 shows an example of SCI transmit operation in asynchronous mode. Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data 1 Idle (mark) state TDRE TEND TXI interrupt request generated TXI interrupt handler writes data to SCTDR and clears TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14.9 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for receiving serial data. The procedure for receiving serial data after enabling the SCI for reception is: 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and FER bits in SCSSR to identify the error. After executing the necessary error handling, clear ORER, PER and FER to 0. Receiving cannot resume if ORER, PER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0 before the stop bit of the current frame is received. Rev. 5.00, 09/03, page 461 of 760 Start of reception Read ORER, PER, and FER bits in SCSSR Yes (1) (2) Error handling PER FER ORER = 1? No Read RDRF bit in SCSSR No RDRF = 1? Yes Read receive data from SCRDR (3) and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.10 Sample Flowchart for Receiving Serial Data Rev. 5.00, 09/03, page 462 of 760 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR to 0 Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 End Figure 14.10 Sample Flowchart for Receiving Serial Data (cont) Rev. 5.00, 09/03, page 463 of 760 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SCSMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from SCRSR into SCRDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in SCRDR. If one of the checks fails (receive error), the SCI operates as indicated in table 14.12. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 14.12 Receive Error Conditions and SCI Operation Receive Error Overrun error Abbreviation ORER Condition Receiving of next data ends while RDRF is still set to 1 in SCSSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SCSMR Data Transfer Receive data not transferred from SCRSR into SCRDR Receive data transferred from SCRSR into SCRDR Receive data transferred from SCRSR into SCRDR Framing error Parity error FER PER Rev. 5.00, 09/03, page 464 of 760 Figure 14.11 shows an example of SCI receive operation in asynchronous mode. Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data 1 Idle (mark) state RDRF RXI interrupt request generated 1 frame RXI interrupt handler reads data and clears RDRF bit to 0 ERI interrupt request generated by framing error FER Figure 14.11 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 14.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 14.12 shows an example of communication among processors using the multiprocessor format. Rev. 5.00, 09/03, page 465 of 760 Transmitting station Serial communication line Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data H'01 (MPB = 1) ID transmit cycle: specifies receiving station H'AA (MPB = 0) Data transmit cycle: data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 14.12 Communication Among Processors Using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 14.11. Clock: See the description in the asynchronous mode section. Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For SCPCR and SCPDR settings, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR). Rev. 5.00, 09/03, page 466 of 760 Start of transmission Read TDRE bit in SCSSR (1) No TDRE = 1? Yes Write transmit data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 Transmission ended? Yes Read TEND bit in SCSSR No (2) TEND = 1? Yes Break output? Yes (3) Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End of transmission No No Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 5.00, 09/03, page 467 of 760 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and transfers this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0-bit is output. b. Transmit data: Seven or eight bits are output, LSB first. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit: One or two 1-bits (stop bits) are output. e. Marking: Output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI transfers data from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SCSSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 14.14 shows SCI transmission with a multiprocessor format. Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 D1 Multiprocessor bit Stop Data bit D7 0/1 1 1 Serial data Start bit 0 1 Idle (mark) state TDRE TEND TXI interrupt request generated Writes data to TDR with the TXI interrupt processing routine and clears TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14.14 Example of SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 5.00, 09/03, page 468 of 760 Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. 2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 3. SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data from the receive data register (SCRDR). 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SCSSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Rev. 5.00, 09/03, page 469 of 760 Start of reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR No (1) Yes (2) RDRF = 1? Yes Read receive data from SCRDR No Is ID the station's ID? Yes Read ORER and FER bits in SSCSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR RDRF = 1? Yes Read receive data from SCRDR No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. (3) Error handling (4) No Yes Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data Rev. 5.00, 09/03, page 470 of 760 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR to 0 Yes Clear ORER and FER bits in SCSSR to 0 End Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev. 5.00, 09/03, page 471 of 760 Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. Data (ID1) D0 D1 D7 Stop Start Data bit (data 1) MPB bit 1 1 0 D0 D1 D7 1 Serial data MPIE Start bit 0 Stop MPB bit 0 1 1 Idle (mark) state RDRF RDR value RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID1 ID is not station's ID, so MPIE bit is set to 1 again No RXI interrupt generated; RDR state is maintained Example: Own ID does not match data Figure 14.16 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 5.00, 09/03, page 472 of 760 1 Serial data MPIE Start bit 0 Data (ID2) D0 D1 D7 MPB 1 Data Stop Start bit bit (Data 2) 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Idle (mark) state RDRF RDR value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Example: Own ID matches data RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID is that of station, MPIE bit so reception continues set to 1 unchanged and data again is received by RXI interrupt handler Figure 14.16 Example of SCI Receive Operation (cont) (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 5.00, 09/03, page 473 of 760 14.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 14.17 shows the general format in synchronous serial communication. One unit of communication data (character or frame) * Serial clock * LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care Note: * High except in continuous transmitting or receiving Figure 14.17 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Rev. 5.00, 09/03, page 474 of 760 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). See table 14.10. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2character units, so a 16-pulse serial clock is output. To receive in 1-character units, select an external clock source. Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Figure 14.18 shows a sample flowchart for initializing the SCI. The procedure for initializing the SCI is: 1. Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 2. Select transmit/receive format in the serial mode register (SCSMR). 3. Write the value corresponding to the bit rate in the bit rate register (SCBRR) (not necessary if an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE and MPIE. Setting TE and RE allows use of the TxD and RxD pins. Rev. 5.00, 09/03, page 475 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) (1) Set transmit/receive format in SCSMR (2) Set value in SCBRR Wait Has a 1-bit period elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) No (3) End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.18 Sample Flowchart for SCI Initialization Transmitting Serial Data (Synchronous Mode): Figure 14.19 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. Rev. 5.00, 09/03, page 476 of 760 Start of transmission Read TDRE bit in SCSSR No (1) TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Yes Read TEND bit in SCSSR No (2) TEND = 1? Yes Clear TE bit in SCSCR to 0 End of transmission No Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.19 Sample Flowchart for Transmitting Serial Data Rev. 5.00, 09/03, page 477 of 760 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from SCTDR into SCTSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SCSSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 14.20 shows an example of SCI transmit operation. Transfer direction Serial clock LSB Bit 0 MSB Bit 7 Serial data Bit 1 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt handler writes data to TDR and clears TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14.20 Example of SCI Transmit Operation Rev. 5.00, 09/03, page 478 of 760 Receiving Serial Data (Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is: 1. Receive error handling: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 2. SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Rev. 5.00, 09/03, page 479 of 760 Start of reception Read ORER bit in SCSSR Yes ORER = 1? No (1) Read RDRF bit in SCSSR No (2) Error handling RDRF = 1? Yes Read receive data from SCRDR (3) and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 14.21 Sample Flowchart for Receiving Serial Data Rev. 5.00, 09/03, page 480 of 760 Error handling No ORER = 1? Yes Overrun error handling Clear ORER bit in SCSSR to 0 End Figure 14.21 Sample Flowchart for Receiving Serial Data (cont) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from SCRSR into SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 14.12. This state prevents further transmission or reception. While receiving, the RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 14.22 shows an example of SCI receive operation. Rev. 5.00, 09/03, page 481 of 760 Transfer direction Serial clock Serial data RDRF ORER Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated RXI interrupt handler reads data and clears RDRF bit to 0 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 14.22 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure for setting the SCI to transmit and receive serial data simultaneously is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 2. Receive error handling: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue transmitting and receiving serial data: Read the RDRF bit and SCRDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. Rev. 5.00, 09/03, page 482 of 760 Start of transmission/reception Read TDRE bit in SCSSR No (1) TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR Yes (2) Error processing ORER = 1? No Read RDRF bit in SCSSR No (3) RDRF = 1? Yes Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 (4) No All data transmitted/received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission/reception Notes: 1. Numbers in parentheses refer to steps in the preceding procedure description. 2. In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously. Figure 14.23 Sample Flowchart for Transmitting/Receiving Serial Data Rev. 5.00, 09/03, page 483 of 760 14.4 SCI Interrupts The SCI has four interrupt sources transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SCSSR is set to 1. RXI is requested when the RDRF bit in SCSSR is set to 1. ERI is requested when the ORER, PER, or FER bit in SCSSR is set to 1. TEI is requested when the TEND bit in SCSSR is set to 1. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 14.13 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority When Reset Is Cleared High See section 4, Exception Handling, for priorities and the relationship to non-SCI interrupts. Rev. 5.00, 09/03, page 484 of 760 14.5 Usage Notes Note the following points when using the SCI. SCTDR Writing and TDRE Flag: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit state. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 14.14 indicates the state of SCSSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the SCRSR contents cannot be transferred to SCRDR, so receive data is lost. Table 14.14 SCSSR Status Flags and Transfer of Receive Data SCSSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error RDRF 1 0 0 1 1 0 ORER 1 0 0 1 1 0 1 FER PER 0 1 0 1 0 1 1 0 0 1 0 1 1 1 Receive Data Transfer SCRSR SCRDR X O O X X O X Overrun error + framing error + parity error 1 X: Receive data is not transferred from SCRSR to SCRDR. O: Receive data is transferred from SCRSR to SCRDR. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: The TxD pin I/O condition and level can be determined by means of the SCP0DT bit in the port SC data register (SCPDR) and bits SCP0MD0 and SCP0MD1 in the port SC control register (SCPCR). This feature can be used to send breaks. To send a break during serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. Rev. 5.00, 09/03, page 485 of 760 TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag is confirmed. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse (figure 14.24). 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode Rev. 5.00, 09/03, page 486 of 760 The receive margin in asynchronous mode can therefore be expressed as in equation 1. Equation 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5)F - 2N N Where: M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0 to 1.0) L = Frame length (L = 9 to 12) F = Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as in equation 2. Equation 2: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Notes on Synchronous External Clock Mode: * Do not set TE = RE = 1 until at least four clocks after external clock SCK has changed from 0 to 1. * Set TE = RE = 1 only when external clock SCK is 1. * When receiving, RDRF is set to 1 when RE is set to zero 2.5-3.5 clocks after the rising edge of the SCK input of the D7 bit in RxD, but data cannot be copied to SCRDR. Note on Synchronous Internal Clock Mode: When receiving, RDRF is set to 1 when RE is cleared to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but data cannot be copied to SCRDR. Rev. 5.00, 09/03, page 487 of 760 Rev. 5.00, 09/03, page 488 of 760 Section 15 Smart Card Interface 15.1 Overview As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC7816-3 (Identification Card) standard. Register settings are used to switch between the normal serial communication interface and the smart card interface. 15.1.1 Features The smart card interface has the following features: * Asynchronous mode Data length: 8 bits Parity bit generation and check Receive mode error signal detection (parity error) Transmit mode error signal detection and automatic re-transmission of data Supports both direct convention and inverse convention * Bit rate can be selected using on-chip baud rate generator. * Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently. Rev. 5.00, 09/03, page 489 of 760 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR RxD SCRSR SCTSR Baud rate generator P P/4 P/16 P/64 TxD Parity generation Parity check Clock External clock TXI RXI ERI SCK SCI Legend SCSCMR: SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 15.1 Block Diagram of Smart Card Interface Rev. 5.00, 09/03, page 490 of 760 15.1.3 Pin Configuration Table 15.1 summarizes the smart card interface pins. Table 15.1 Smart Card Interface Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 I/O Output Input Output Function Clock output Receive data input Transmit data output 15.1.4 Smart Card Interface Registers Table 15.2 summarizes the registers used by the smart card interface. The SCSMR, SCBRR, SCSCR, SCTDR, and SCRDR registers are the same as for the normal SCI function. They are described in section 14, Serial Communication Interface (SCI). Table 15.2 Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Abbreviation R/W SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR R/W R/W R/W R/W R R/W 3 Initial Value* Address Access Size 8 8 8 8 8 8 8 H'00 H'FF H'00 H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A 2 H'FF *1 H'84 R/(W) H'00 H'00* H'FFFFFE8C Notes: 1. Only 0 can be written, to clear the flags. 2. Bits 0, 2, and 3 are cleared. The value of the other bits is undefined. 3. Initialized by a power-on or manual reset. Rev. 5.00, 09/03, page 491 of 760 15.2 Register Descriptions This section describes the registers added for the smart card interface and the bits whose functions are changed. 15.2.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby mode. Bit: Initial value: R/W: 7 -- -- R 6 -- -- R 5 -- -- R 4 -- -- R 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- -- R 0 SMIF 0 R/W Bits 7 to 4 and 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 1 Description Contents of SCTDR are transferred LSB-first, and receive data is stored in SCRDR LSB-first (Initial value) Contents of SCTDR are transferred MSB-first, and receive data is stored in SCRDR MSB-first Bit 2--Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the data. This function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. SINV does not affect the logic level of the parity bit. See section 15.3.4, Register Settings, for information on how parity is set. Bit 2: SINV 0 1 Description Contents of SCTDR are transferred unchanged, and receive data is stored in SCRDR unchanged (Initial value) Contents of SCTDR are inverted before transfer, and receive data is inverted before storage in SCRDR Rev. 5.00, 09/03, page 492 of 760 Bit 0--Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 : SMIF 0 1 Description Smart card interface function disabled Smart card interface function enabled (Initial value) 15.2.2 Serial Status Register (SCSSR) In smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed. Bit: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W ORER FER/ERS Note: Only 0 can be written, to clear the flag. Bit 7--Transmit Data Register Empty (TDRE) Bit 6--Receive Data Register Full (RDRE) Bit 5--Overrun Error (ORER) These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. Bit 4--Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the state of the error signal returned from the receiving side during transmission. The smart card interface cannot detect framing errors. Bit 4: ERS 0 Description Receiving ended normally with no error signal [Clearing conditions] (1) By a reset or in standby mode (2) Cleared by reading ERS when ERS = 1, then writing 0 to ERS 1 An error signal indicating a parity error was transmitted from the receiving side [Setting condition] If the error signal sampled is low Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0. (Initial value) Rev. 5.00, 09/03, page 493 of 760 Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. Bit 2: TEND 0 Description Transmission is in progress [Clearing condition] Cleared by reading TDRE when TDRE = 1, then writing 0 to TDRE 1 End of transmission [Setting conditions] (1) the chip is reset or enters standby mode, (2) the TE bit in SCSCR is 0 and the FER/ERS bit is also 0, (3) the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or (4) the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. Note: etu: Elementary Time Unit (time for transfer of 1 bit). (Initial value) 15.3 15.3.1 Operation Overview The primary functions of the smart card interface are described below. 1. Each frame consists of 8-bit data and 1 parity bit. 2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: time for transfer of 1 bit) from the end of the parity bit to the start of the next frame. 3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. During transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. Only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available. Rev. 5.00, 09/03, page 494 of 760 15.3.2 Pin Connections Figure 15.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply VCC side with a register. When using the clock generated by the smart card interface on an IC card, input the SCK pin output to the IC card's CLK pin. This connection is not necessary when the internal clock is used on the IC card. Use the chip's port output as the reset signal. Apart from these pins, power and ground pin connections are usually also required. Note: When the IC card is not connected and both RE and TE are set to 1, closed communication is possible and auto-diagnosis can be performed. VCC TxD Data line RxD SCK Px (port) Clock line IO CLK LSI Reset line RST IC card Connected device Figure 15.2 Pin Connection Diagram for Smart Card Interface Rev. 5.00, 09/03, page 495 of 760 15.3.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected. With no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output With parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Ds: D0-D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 15.3 Data Format for Smart Card Interface The operating sequence is: 1. The data line is high-impedance when not in use and is fixed high with a pull-up register. 2. The transmitting side starts one frame of data transmission. The data frame starts with a start bit (Ds, low level). The start bit is followed by eight data bits (D0-D7) and a parity bit (Dp). 3. On the smart card interface, the data line returns to high-impedance after this. The data line is pulled high with a pull-up register. 4. The receiving side checks parity. When the data is received normally with no parity errors, the receiving side then waits to receive the next data. When a parity error occurs, the receiving side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving station returns the signal line to high-impedance after outputting the error signal for a specified period. The signal line is pulled high with a pull-up register. Rev. 5.00, 09/03, page 496 of 760 5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 Register Settings Table 15.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value. The settings for the other bits are described below. Table 15.3 Register Settings for Smart Card Interface Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C Bit 7 C/A BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 FER/ ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Note: Dashes indicate unused bits. 1. Setting the serial mode register (SCSMR): The C/A bit selects the setting timing of the TEND flag, and selects the clock output state in combination with bits CKE1 and CKE0 in the serial control register (SCSCR). Clear the O/E bit to 0 if the IC card uses the direct convention, and set it to 1 if the card uses the inverse convention. Select the on-chip baud rate generator clock source with the CKS1 and CKS0 bits (see section 15.3.5, Clock). 2. Setting the bit rate register (SCBRR): Set the bit rate. See section 15.3.5, Clock, to see how to calculate the set value. 3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do for the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The CKE0 bit specifies the clock output. When no clock is output, clear CKE0 to 0; when a clock is output, set CKE0 to 1. 4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both cleared to 0 for IC cards that use the direct convention, and both set to 1 when the inverse convention is used. The SMIF bit is set to 1 for the smart card interface. Figure 15.4 shows sample waveforms for register settings of the two types of IC cards (direct convention and inverse convention) and their start characters. In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and communication is LSB-first. The start character data is H'3B. Parity is even (from the smart card standard), and so the parity bit is 1. Rev. 5.00, 09/03, page 497 of 760 In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), and so the parity bit is 0, which corresponds to state Z. Only data bits D7-D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in SCSMR to odd parity mode. This applies to both transmission and reception. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State a. Direct convention (SDIR, SINV, and O/E are all 0) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State b. Inverse convention (SDIR, SINV, and O/E are all 1) Figure 15.4 Waveform of Start Character 15.3.5 Clock Only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. The bit rate for the clock is set by the bit rate register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is calculated using the equation below. Table 15.5 shows sample bit rates. If clock output is then selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the SCK0 pin. B= P x 106 1488 x 22n-1 x (N + 1) Where: N = Value set in SCBRR (0 N 255) B = Bit rate (bits/s) P = Peripheral module operating frequency (MHz) n = 0 to 3 (table 15.4) Rev. 5.00, 09/03, page 498 of 760 Table 15.4 Relationship of n to CKS1 and CKS0 n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 15.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0) P (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 Note: The bit rate is rounded to one decimal place. Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the bit rate. N is an integer in the range 0 N 255, specifying a smallish error. N= P x 106 - 1 1488 x 22n-1 x B Table 15.6 Examples of SCBRR Settings for Bit Rate B (Bits/s) (n = 0) (MHz) (9600 Bits/s) 7.1424 N 0 Error 0.00 N 1 10.00 Error 30.00 N 1 10.7136 Error 25.00 N 1 13.00 Error 8.99 N 1 14.2848 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99 Rev. 5.00, 09/03, page 499 of 760 Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Maximum Bit Rate (Bits/s) 9600 13441 14400 17473 19200 21505 24194 N 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 The bit rate error is found as follows: Error (%) = ( P x 106 - 1) x 100 1488 x 22n-1 x B x (N + 1) Table 15.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. Table 15.8 Register Set Values and SCK Pin Register Value Setting 1 1* SCK Pin CKE0 0 Output Port State Determined by setting of port register SCP1MD1 and SCP1MD0 bits SCK (serial clock) output state Low output High output Low output state SCK (serial clock) output state High output state SCK (serial clock) output state SMIF 1 C/A A 0 CKE1 0 1 2 2* 0 1 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 1 3 *2 Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit should be cleared to 0. 2. The clock duty remains constant despite stopping and starting of the clock by modification of the CKE0 bit. Rev. 5.00, 09/03, page 500 of 760 15.3.6 Data Transmission and Reception Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 15.5 shows a flowchart of the initialization process. 1. Clear TE and RE in the serial control register (SCSCR) to 0. 2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR). 3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits) in the serial mode register (SCSMR). At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). When the SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI pins and become high-impedance. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR). 6. Set the clock source select bits (CKE1 and CKE0 bits) in the serial control register (SCSCR). Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCK pin. 7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and RE bits simultaneously unless performing auto-diagnosis. Rev. 5.00, 09/03, page 501 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Clear FER/ERS, PER and ORER flags in SCSSR to 0 Set parity in O/E bit, set clock in CKS1 and CKS0 bits, and set C/A, in SCSMR Set SMIF, SDIR, and SINV bits in SCSMR Set value in SCBRR Set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0, in SCSCR Wait Has a 1-bit interval elapsed? Yes Set TIE, RIE, TE, and RE bits in SCSCR (7) No (1) (2) (3) (4) (5) (6) End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 15.5 Initialization Flowchart (Example) Rev. 5.00, 09/03, page 502 of 760 Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 15.6. 1. Initialize the smart card interface mode as described in Initialization above. 2. Check that the FER/ERS bit in SCSSR is cleared to 0. 3. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1. 4. Write the transmit data into SCTDR, clear the TDRE flag to 0 and start transmitting. The TEND flag will be cleared to 0. 5. To transmit more data, return to step 2. 6. To end transmission, clear the TE bit to 0. This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end of transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error occurs in transmission. See Interrupt Operation below for more information. Rev. 5.00, 09/03, page 503 of 760 Start Initialize (1) Start of transmission (2) No FER/ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 No All data transmitted? Yes No (5) (4) (3) FER/ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR to 0 (6) End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 15.6 Transmission Flowchart Rev. 5.00, 09/03, page 504 of 760 Serial Data Reception: The processing procedures in smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 15.7. 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error handling procedures. 3. Repeat steps 2 and 3 until the RDRF flag is set to 1. 4. Read the receive data from SCRDR. 5. To receive more data, clear the RDRF flag to 0 and return to step 2. 6. To end reception, clear the RE bit to 0. This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of reception. When an error occurs during reception and either the ORER or PER flag is set to 1, a communication error interrupt (ERI) will be requested. See Interrupt Operation below for more information. The received data will be transferred to SCRDR even when a parity error occurs during reception and PER is set to 1, so this data can still be read. Rev. 5.00, 09/03, page 505 of 760 Start Initialize (1) Start of reception (2) No ORER = 0 or PER = 0? Yes Error handling No RDRF = 1? Yes Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 (6) (5) (4) (3) End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 15.7 Reception Flowchart (Example) Rev. 5.00, 09/03, page 506 of 760 Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization, clearing TE to 0, and setting RE to 1. The TEND flag can be used to check if transmission is completed. Interrupt Operation: In the smart card interface mode, there are three types of interrupts: transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode, the transmit-end interrupt (TEI) cannot be requested. Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI interrupt (table 15.9). Table 15.9 Smart Card Mode Operating State and Interrupt Sources Mode Transmit mode Receive mode State Normal Error Normal Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI 15.4 Usage Notes When the SCI is used as a smart card interface, be sure that all criteria in sections 15.4.1, Receive Data Timing and Receive Margin in Asynchronous Mode and 15.4.2, Retransmission are applied. 15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI runs on a base clock with a frequency of 372 times the transfer rate. During reception, the SCI samples the falling of the start bit using the base clock to achieve internal synchronization. Receive data is latched internally at the rising edge of the 186th base clock cycle (figure 15.8). Rev. 5.00, 09/03, page 507 of 760 372 clock cycles 186 clock cycles 0 185 371 0 185 371 0 Base clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: M = (0.5 - 1 D - 0.5 (1 + F) x 100% ) - (L - 0.5)F - 2N N Where: M = Receive margin (%) N = Ratio of bit rate to clock (N = 372) D = Clock duty (D = 0 to 1.0) L = Frame length (L = 10) F = Absolute value of clock frequency deviation Using this equation, the receive margin when F = 0 and D = 0.5 is as follows: M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 5.00, 09/03, page 508 of 760 15.4.2 Retransmission (Receive and Transmit Modes) Retransmission when SCI is in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the PER bit before the next parity bit is sampled. 2. The RDRF bit in SCSSR is not set in the frame that caused the error. 3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set. 4. When the received parity bit is checked and no error is found, reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an RXI interrupt is requested. 5. When a normal frame is received, the pin maintains a three-state state when it transmits the error signal. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n + 1 Ds D0 D1 D2 D3 D4 5 RDRF 2 PER 1 3 4 Figure 15.9 Retransmission in SCI Receive Mode Rev. 5.00, 09/03, page 509 of 760 Retransmission when SCI is in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is sampled. 2. The TEND bit in SCSSR is not set in the frame that received the error signal indicating the error. 3. The FER/ERS bit in SCSSR is not set when no error signal is returned from the receiving side. 4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1 when the transmission of the frame that includes the retransmission is considered completed. If the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n + 1 Ds D0 D1 D2 D3 D4 TDRE Transfer from SCTDR to SCTSR TEND 2 FER/ERS 1 Transfer from SCTDR to SCTSR Transfer from SCTDR to SCTSR 4 3 Figure 15.10 Retransmission in SCI Transmit Mode Rev. 5.00, 09/03, page 510 of 760 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview The SH7709S has a two-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception that enable the SH7709S to perform efficient high-speed continuous communication. 16.1.1 Features * Asynchronous serial communication: Serial data communication is performed by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity and framing errors Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the port SC data register (SCPDR) when a framing error occurs. * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receiveFIFO-data-full interrupt. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * On-chip modem control functions (RTS and CTS) * The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be ascertained. * A time-out error (DR) can be detected when receiving. Rev. 5.00, 09/03, page 511 of 760 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Bus interface Module data bus Internal data bus SCFRDR2 (16 stages) Receive buffer RxD TxD SCRSR SCFTDR2 (16 stages) Transmit buffer SCTSR Parity generation Parity check SCPCR SCFDR SCFDR2 SCFCR2 SCSSR2 SCSCR2 SCSMR2 Transmit/ receive control SCBRR Baud rate generator P P/4 P/16 P/64 Clock External clock TEI TXI RXI BRI SCK SCIF Legend SCRSR: SCFRDR2: SCTSR: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register 2 Transmit shift register Transmit FIFO data register 2 Serial mode register 2 Serial control register 2 SCSSR2: SCBRR2: SCFCR2: SCFDR2: SCPDR: SCPCR: Serial status register 2 Bit rate register 2 FIFO control register 2 FIFO data count register 2 Port SC data register Port SC control register Figure 16.1 Block Diagram of SCIF Rev. 5.00, 09/03, page 512 of 760 Figures 16.2 to 16.4 show the SCIF I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR). Reset R D SCP5MD0 Q C PCRW Reset Q R D Internal data bus SCP5MD1 C PCRW Reset SCPT[5]/SCK2 R Q D SCP5DT1 C PDRW SCIF Clock input enable Output enable Serial clock output PDRR* Serial clock input Legend PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK2 pin, clear the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP5MD1 bit in SCSPR to 1 (see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)). Figure 16.2 SCPT[5]/SCK2 Pin Rev. 5.00, 09/03, page 513 of 760 Reset R D SCP4MD0 Q C PCRW Reset Q R D Internal data bus SCP4MD1 C PCRW Reset SCPT[4]/TxD2 R Q D SCP4DT1 C PDRW Output enable Serial transmission output SCIF Legend PCRW: SCPCR write PDRW: SCPDR write Figure 16.3 SCPT[4]/TxD2 Pin Rev. 5.00, 09/03, page 514 of 760 SCIF SCPT[4]/RxD2 Serial receive data PDRR* Internal data bus Legend PDRR: SCPDR read Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCPT[4]/RxD2 Pin 16.1.3 Pin Configuration The SCIF has the serial pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin Abbreviation SCK2 RxD2 TxD2 RTS2 CTS2 I/O I/O Input Output Output Input Function Clock I/O Receive data input Transmit data output Request to send Clear to send Rev. 5.00, 09/03, page 515 of 760 16.1.4 Register Configuration Table 16.2 summarizes the SCIF internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 16.2 SCIF Registers Register Name Serial mode register 2 Bit rate register 2 Serial control register 2 Abbreviation R/W SCSMR2 SCBRR2 SCSCR2 R/W R/W R/W W 1 Initial Value Address H'00 H'FF H'00 -- Access size H'04000150 8 bits 2 (H'A4000150)* H'04000152 8 bits 2 (H'A4000152)* H'04000154 8 bits 2 (H'A4000154)* H'04000156 8 bits 2 (H'A4000156)* H'04000158 16 bits 2 (H'A4000158)* H'0400015A 8 bits 2 (H'A400015A)* H'0400015C 8 bits 2 (H'A400015C)* H'0400015E 16 bits 2 (H'A400015E)* Transmit FIFO data register 2 SCFTDR2 Serial status register 2 SCSSR2 R/(W)* H'0060 R R/W R Undefined H'00 H'0000 Receive FIFO data register 2 SCFRDR2 FIFO control register 2 FIFO data count register 2 SCFCR2 SCFDR2 Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 516 of 760 16.2 16.2.1 Register Descriptions Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- 16.2.2 Receive FIFO Data Register (SCFRDR) The 16-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data is lost. Bit: R/W: 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 R 16.2.3 Transmit Shift Register (SCTSR) The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Rev. 5.00, 09/03, page 517 of 760 16.2.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a FIFO register comprising sixteen 8-bit stages that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can always write to SCFTDR. When SCFTDR is full of transmit data (16 stages), no more data can be written. If writing of new data is attempted, the data is ignored. Bit: R/W: 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W 16.2.5 Serial Mode Register (SCSMR) The serial mode register (SCSMR) is an 8-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'00 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 -- 0 R 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. Bit 6: CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. Rev. 5.00, 09/03, page 518 of 760 Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data. Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked* (Initial value) Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. E The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored when parity addition and checking is disabled. Bit 4: O/E E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 1 Description One stop bit* 2 Two stop bits* 1 (Initial value) Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1-bits are added at the end of each transmitted character. Bit 2--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 519 of 760 Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the onchip baud rate generator. According to the setting of the CKS1 and CKS0 bits four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.2.8, Bit Rate Register (SCBRR). Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Note: P: Peripheral clock Description P P/4 P/16 P/64 (Initial value) 16.2.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCIF transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode. Bit: Initial value: R/W: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 -- 0 R 2 -- 0 R 1 CKE1 0 R/W 0 CKE0 0 R/W Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial FIFO status register (SCFSR) is set to1. Bit 7: TIE 0 1 Description Transmit-FIFO-data-empty interrupt request (TXI) is disabled* Transmit-FIFO-data-empty interrupt request (TXI) is enabled (Initial value) Note: * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. Rev. 5.00, 09/03, page 520 of 760 Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in the receive FIFO register becomes more than the specified receive trigger number, and when the RDRF flag in SCSSR is set to1. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break interrupt (BRI) requests are disabled* (Initial value) Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. With the RDF flag, read 1 from the RDF flag and clear it to 0, after reading receive data from SCRDR until the quantity of receive data becomes less than the specified receive trigger number. Bit 5--Transmit Enable (TE): Enables or disables the SCIF serial transmitter. Bit 5: TE 0 1 Description Transmitter disabled Transmitter enabled* (Initial value) Note: * Serial transmission starts after writing of transmit data into SCFTDR2. Select the transmit format in SCSMR2 and SCFCR2 and reset the TFIFO before setting TE to 1. Bit 4--Receive Enable (RE): Enables or disables the SCIF serial receiver. Bit 4: RE 0 1 Description Receiver disabled* 2 Receiver enabled* 1 (Initial value) Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected. Select the receive format in SCSMR2 before setting RE to 1. Bits 3 and 2--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00, 09/03, page 521 of 760 Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 = 0). The CKE0 setting is ignored when an external clock source is selected (CKE1 = 1). Before selecting the SCIF operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCIF clock source, see table 16.7 in section 16.3, Operation. Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 Description Internal clock, SCK pin used for input pin (input signal is ignored) (Initial value) *1 Internal clock, SCK pin used for clock output 2 External clock, SCK pin used for clock input* 2 External clock, SCK pin used for clock input* Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate. 16.2.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is a 16-bit register. The upper 8 bits indicate the number of receive errors in the SCFRDR data, and the lower 8 bits indicate the SCIF operating state. The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, OPER, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCSSR is initialized to H'0060 by a reset and in standby or module standby mode. Lower 8 bits: Initial value: R/W: 7 ER 0 R/(W)* 6 TEND 1 R/(W)* 5 TDFE 1 R/(W)* 4 BRK 0 R/(W)* 3 FER 0 R 2 PER 0 R 1 RDF 0 R/(W)* 0 DR 0 R/(W)* Note: * The only value that can be written is 0 to clear the flag. Rev. 5.00, 09/03, page 522 of 760 Bit 7--Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. Bit 7: ER 0 Description 1 Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) By a power-on reset or in standby mode ER is cleared to 0 when the chip is reset or enters standby mode 1 (2) When 0 is written after 1 is read from ER 2 A framing error or parity error has occurred* [Setting conditions] (1) ER is set to 1 when the stop bit is 0 after checking whether or not the last 2 stop bit of the received data is 1 at the end of one data receive operation* (2) When the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCRDR includes a receive error can be detected by the FER and PER bits in SCSSR. 2. In stop mode, only the first stop bit is checked; the second stop bit is not checked. Bit 6--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. Bit 6: TEND 0 Description Transmission is in progress [Clearing condition] When data is written in SCFTDR 1 End of transmission [Setting conditions] (1) When the chip is reset or enters standby mode, when TE is cleared to 0 in the serial control register (SCSCR) (2) When SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted (Initial value) Rev. 5.00, 09/03, page 523 of 760 Bit 5--Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. Bit 5: TDFE 0 Description The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number (Initial value) [Clearing condition] TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR, or when software reads TDFE after it has been set to 1, then writes 0 to TDFE 1 The quantity of transmit data in SCFTDR is less than the specified transmission trigger number* [Setting conditions] (1) TDFE is set to 1 by a reset or in standby mode (2) When the quantity of transmit data in SCFTDR becomes less than the specified transmission trigger number as a result of transmission Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFTDR. Bit 4--Break Detection (BRK): Indicates that a break signal has been detected in receive data. Bit 4: BRK 0 Description No break signal received [Clearing conditions] (1) BRK is cleared to 0 when the chip is reset or enters standby mode 1 (2) When software reads BRK after it has been set to 1, then writes 0 to BRK Break signal received* [Setting conditions] (1) BRK is set to 1 when data including a framing error is received (2) A framing error occurs with space 0 in the subsequent receive data Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. The receive data of a frame in which a break signal is detected is transferred to SCFRDR. After this, however, no receive data is transferred until a break ends with the received signal being mark 1, and the next data is received. (Initial value) Rev. 5.00, 09/03, page 524 of 760 Bit 3--Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR). Bit 3: FER 0 Description No receive framing error occurred in the data read from SCFRDR (Initial value) [Clearing conditions] (1) When the chip undergoes a power-on reset or enters standby mode (2) When no framing error is present in the data read from SCFRDR 1 A receive framing error occurred in the data read from SCFRDR [Setting condition] When a framing error is present in the data read from SCFRDR Bit 2--Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data register (SCFRDR). Bit 2: PER 0 Description No receive parity error occurred in the data read from SCFRDR [Clearing conditions] (1) When the chip undergoes a power-on reset or enters standby mode (2) When no parity error is present in the data read from SCFRDR 1 A receive framing error occurred in the data read from SCFRDR [Setting condition] When a parity error is present in the data read from SCFRDR (Initial value) Rev. 5.00, 09/03, page 525 of 760 Bit 1--Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR). Bit 1: RDF 0 Description The quantity of transmit data written to SCFRDR is less than the specified receive trigger number (Initial value) [Clearing conditions] (1) By a power-on reset or in standby mode (2) When the quantity of receive data in SCFRDR is less than the specified receive trigger value and 1 is read from RDF, which is then cleared to 0 1 The quantity of receive data in SCFRDR is greater than the specified receive trigger number [Setting condition] When a quantity of receive data greater than the specified receive trigger number is stored in SCFRDR* Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 is the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFTDR. Bit 0--Receive Data Ready (DR): Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 etu from the last stop bit. Bit 0: DR 0 Description Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally (Initial value) [Clearing conditions] (1) When the chip undergoes a power-on reset or enters standby mode (2) When software reads DR after it has been set to 1, then writes 0 to DR 1 Next receive data has not been received [Setting condition] When SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 etu from the last stop bit* Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit) Rev. 5.00, 09/03, page 526 of 760 Upper 8 bits: Initial value: R/W: 15 PER3 0 R 14 PER2 0 R 13 PER1 0 R 12 PER0 0 R 11 FER3 0 R 10 FER2 0 R 9 FER1 0 R 8 FER0 0 R Bits 15 to 12--Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR. Bits 11 to 8--Number of Framing Errors 3 to 0 (FER3 to FER0): Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 represents the number of framing errors in SCFRDR. 16.2.8 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The SCBRR setting is calculated as follows: Asynchronous mode: N= B: N: P: n: P 64 x 2 2n - 1 xB x 106 - 1 Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.) Rev. 5.00, 09/03, page 527 of 760 Table 16.3 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 P (N+1) x 64 x 22n-1 x B CKS1 0 0 1 1 CKS0 0 1 0 1 Note: The bit rate error is given by the following formula: Error (%) = x 106 - 1 x 100 Table 16.4 lists examples of SCBRR settings. Table 16.4 Bit Rates and SCBRR Settings P (MHz) 2 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 0 Error (%) n % -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 Rev. 5.00, 09/03, page 528 of 760 P (MHz) 3 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 47 23 11 5 3 2 3.6864 Error (%) n % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -7.84 0.00 P (MHz) 4.9152 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) n % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) n % -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 Rev. 5.00, 09/03, page 529 of 760 P (MHz) 6.144 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) n % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 P (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 1 Error (%) % 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 1.73 0.00 1.73 n N 212 155 77 155 77 38 19 9 4 2 9 12 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 2 1 1 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 7.3728 Error (%) n % -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 -0.26 2 2 2 1 1 0 0 0 0 0 -0.25 1 1 1 0 0 0 0 0 0 0 -1.36 0 -1.70 0 -2.34 0 Rev. 5.00, 09/03, page 530 of 760 P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 3 0 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 3 0 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 8.51 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 4 0 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 6.67 22.9 n 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 4 0 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 8.51 25.0 -1.70 0 -1.70 0 -7.84 0 P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 6 1 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 3 2 2 1 1 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 6 1 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 7 1 Error (%) % 0.31 0.46 0.46 0.46 0.46 n 3 3 2 1 0 N 132 97 194 97 194 97 194 97 48 29 23 7 1 30 Error (%) % 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 1.73 -6.25 -0.44 3 -0.08 2 -0.08 1 -0.08 0 -0.61 0 -1.03 0 1.55 0 -2.68 0 -10.3 0 -1.70 0 -4.76 0 -23.2 0 -2.34 0 -6.99 0 -25.0 0 Rev. 5.00, 09/03, page 531 of 760 Table 16.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.6 list the maximum rates for external clock input. Table 16.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 5.00, 09/03, page 532 of 760 Table 16.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Rev. 5.00, 09/03, page 533 of 760 16.2.9 FIFO Control Register (SCFCR) Bit: Initial value: R/W: 7 RTRG1 0 R/W 6 RTRG0 0 R/W 5 TTRG1 0 R/W 4 TTRG0 0 R/W 3 MCE 0 R/W 2 TFRST 0 R/W 1 RFRST 0 R/W 0 LOOP 0 R/W The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bits 7 and 6--Receive FIFO Data Trigger (RTRG1, RTRG0): Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCSSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register (SCFRDR) exceeds the set trigger number shown below. Bit 7: RTRG1 0 0 1 1 Bit 6: RTRG0 0 1 0 1 Receive Trigger Number 1 4 8 14 (Initial value) Bits 5 and 4--Transmit FIFO Data Trigger (TTRG1, TTRG0): Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCSSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. Bit 5: TTRG1 0 0 1 1 Bit 4: TTRG0 0 1 0 1 Transmit Trigger Number 8 (8)* 4 (12) 2 (14) 1 (15) Note: * Initial value. Values in parentheses mean the number of empty bits in SCFTDR when the TDFE flag is set to 1. Rev. 5.00, 09/03, page 534 of 760 Bit 3--Modem Control Enable (MCE): Enables modem control signals CTS and RTS. Bit 3: MCE 0 1 Description Modem signal disabled* Modem signal enabled (Initial value) Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Bit 2--Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. Bit 2: TFRST 0 1 Description Reset operation disabled* Reset operation enabled (Initial value) Note: * Reset is executed in a reset or in standby mode. Bit 1--Receive FIFO Data Register Reset (RFRST): Disables the receive data in the receive FIFO data register and resets the data to the empty state. Bit 1: RFRST 0 1 Description Reset operation disabled* Reset operation enabled (Initial value) Note: * Reset is executed in a reset or in standby mode. Bit 0--Loop-Back Test (LOOP): Internally connects the transmit output pin (TXD) and receive input pin (RXD) and enables loop-back testing. Bit 0: LOOP 0 1 Description Loop back test disabled Loop back test enabled (Initial value) Rev. 5.00, 09/03, page 535 of 760 16.2.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. Upper 8 Bits: Initial value: R/W: 15 -- 0 R 14 -- 0 R 13 -- 0 R 12 T4 0 R 11 T3 0 R 10 T2 0 R 9 T1 0 R 8 T0 0 R The upper 8 bits of SCFDR indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. Lower 8 Bits: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R The lower 8 bits of SCFDR indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. Rev. 5.00, 09/03, page 536 of 760 16.3 16.3.1 Operation Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals. The transmission format is selected in the serial mode register (SCSMR), as shown in table 16.7. The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.8. * Data length is selectable: 7 or 8 bits. * Parity and multiprocessor bits are selectable, as is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO data full, receive data ready, and breaks. * In transmitting, it is possible to detect transmit FIFO data empty. * The number of stored data bytes is indicated for both the transmit and receive FIFO registers. * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency 16 times the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Table 16.7 SCSMR Settings and SCIF Communication Formats SCSMR Settings Mode Asynchronous Bit 6 CHR 0 Bit 5 PE 0 1 1 0 1 Bit 3 STOP 0 1 0 1 0 1 0 1 Set 7-bit Not set Set Data Length 8-bit Parity Bit Not set SCIF Communication Format Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Rev. 5.00, 09/03, page 537 of 760 Table 16.8 SCSCR Settings and SCIF Clock Source Selection SCSCR Settings Mode Asynchronous mode Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 External Clock Source Internal SCIF Transmit/Receive Clock SCK Pin Function SCIF does not use the SCK pin Outputs a clock with a frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate 16.3.2 Serial Operation Transmit/Receive Formats: Table 16.9 lists the eight communication formats that can be selected. The format is selected by settings in the serial mode register (SCSMR). Table 16.9 Serial Communication Formats SCSMR Bits CHR 0 0 0 0 1 1 1 1 PE 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 1 0 1 1 START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data START: Start bit STOP: Stop bit P: Parity bit Rev. 5.00, 09/03, page 538 of 760 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.8). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is 16 times the bit rate. Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCSSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the high impedance state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. Figure 16.5 shows a sample flowchart for initializing the SCIF. The procedure for initializing the SCIF is: 1. Set the clock selection in SCSCR. Be sure to clear bits RIE TIE, TE, and RE to 0. When clock output is selected, the clock is output immediately after SCSCR settings are made. 2. Set the communication format in SCSMR. 3. Write a value corresponding to the bit rate into the bit rate register (SCBRR). (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Rev. 5.00, 09/03, page 539 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set communication format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes (4) No (2) (1) (3) Set RTRG1-0, TTRG1-0, and MCE in SCFCR Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1,and set RIE, TIE, TEIE, and MPIE bits End Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 16.5 Sample Flowchart for SCIF Initialization Rev. 5.00, 09/03, page 540 of 760 * Serial data transmission Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of transmit data bytes that can be written is (16 - transmit trigger set number). 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: To output a break in serial transmission, set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For information on SCPDR and SCPCR, see section 16.2.8, Bit Rate Register (SCBRR). In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of the FIFO data count register (SCFDR). Rev. 5.00, 09/03, page 541 of 760 Start of transmission Read TDFE bit in SCSSR (1) No TDFE= 1? Yes Write transmit data (16 - transmit trigger set number) to SCFTDR, read 1 from TDFE bit and TEND flag in SCSSR, then clear to 0 (2) No All data transmitted? Yes Read TEND bit in SCSSR TEND= 1? Yes Break output? Yes (3) Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 No No End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 16.6 Sample Flowchart for Transmitting Serial Data Rev. 5.00, 09/03, page 542 of 760 In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One-bit 0 is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Rev. 5.00, 09/03, page 543 of 760 Figure 16.7 shows an example of the operation for transmission. Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data 1 Idle (mark) state TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request Figure 16.7 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 16.8 shows an example of the operation when modem control is used. Start bit Serial data TXD CTS 0 D0 D1 D7 Parity Stop bit bit 0/1 Start bit 0 D0 D1 D7 0/1 Rise at this point before stop bit Figure 16.8 Example of Operation Using Modem Control (CTS) C Rev. 5.00, 09/03, page 544 of 760 * Serial data reception Figures 16.9 and 16.10 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. 2. SCIF status check and receive data read : Read the serial status register (SCSSR) and check that RDF = 1, then read the receive data in the receive FIFO data register (SCFRDR), read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading the lower bits of SCFDR. Rev. 5.00, 09/03, page 545 of 760 Start of reception Read ORER, PER, FER flags in SCSSR (1) PER v FER v ORER = 1? No Read RDF flag in SCSSR No Yes Error handling (2) RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 (3) No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description. Figure 16.9 Sample Flowchart for Receiving Serial Data Rev. 5.00, 09/03, page 546 of 760 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored. Error handling (1) No ER = 1? Yes Receive error handling (2) No BRK = 1? Yes Break processing No DR = 1? Yes Read receive data from SCFRDR Clear DR, ER, BRK flags in SCSSR to 0 End Figure 16.10 Sample Flowchart for Receiving Serial Data (cont) Rev. 5.00, 09/03, page 547 of 760 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. c. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: Reception is not suspended when a receive error occurs. 4. If the RIE bit in SCSR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-datafull interrupt (RXI) request is generated. If the RIE bit in SCSR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit in SCSR is set to 1 when the BRK flag changes to 1, a break reception interrupt (BRI) request is generated. Rev. 5.00, 09/03, page 548 of 760 Figure 16.11 shows an example of the operation for reception. Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data D1 1 Idle (mark) state RDF RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error FER Figure 16.11 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output when SCFRDR is empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR is full and reception is not possible. Figure 16.12 shows an example of the operation when modem control is used. Start bit 0 D0 D1 D2 Serial data RXD RTS Parity bit D7 0/1 1 Start 0 Figure 16.12 Example of Operation Using Modem Control (RTS) R Rev. 5.00, 09/03, page 549 of 760 16.4 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.10 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. When data exceeding the transmit trigger number is written to the transmit data register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it. When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed when the RDF flag in SCSSR is set to 1. When receive data less than the receive trigger number is read from the receive data register (SCFRDR) by the DMAC, 1 is read from the RDF flag, after which 0 is written to it to clear it. When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated. When the BRK flag in SCSSR is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR. Table 16.10 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive data FIFO full flag (RDF) or data ready flag (DR) Interrupt initiated by break flag (BRK) Interrupt initiated by transmit FIFO data empty flag (TDFE) DMAC Activation Not possible Possible (RDF only) Not possible Possible Low Priority on Reset Release High See section 4, Exception Handling, for priorities and the relationship to non-SCIF interrupts. Rev. 5.00, 09/03, page 550 of 760 16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written to SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again even after having been cleared to 0. TDFE clearing should therefore be carried out after data exceeding the specified transmit trigger number has been written to SCFTDR. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 2. SCFRDR Reading and RDF Flag: The RDF flag in the serial status register (SCSSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again even after having been cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). 3. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate, so if the BRK flag is cleared to 0 it will be set to 1 again. 4. Sending a Break Signal: The I/O condition and level of the TxD pin are determined by the SCP4DT bit in the port SC data register (SCPDR) and bits SCP4MD0 and SCP4MD1 in the port SC control register (SCPCR). This feature can be used to send a break signal. To send a break signal during serial transmission, clear the SCP4DT bit to 0 (designating low level), then set the SCP4MD0 and SCP4MD1 bits to 0 and 1, respectively, and finally clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. Rev. 5.00, 09/03, page 551 of 760 5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag is confirmed. 6. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.13. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5) F - 2N N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Rev. 5.00, 09/03, page 552 of 760 Equation 2: When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 5.00, 09/03, page 553 of 760 Rev. 5.00, 09/03, page 554 of 760 Section 17 IrDA 17.1 Overview The SH7709S has an on-chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 system and can perform infrared communication. It also can be used as the SCIF by making register settings. 17.1.1 Features * Conforms to the IrDA 1.0 system * Asynchronous serial communication Data length: 8 bits Stop bit length: 1 bit Parity bit: None * On-chip 16-stage FIFO buffers for both transmit and receive operations * On-chip baud rate generator with selectable bit rates * Guard functions to protect the receiver during transmission * Clock supply halted to reduce power consumption when not using the IrDA interface Rev. 5.00, 09/03, page 555 of 760 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the IrDA. Clock input SCK TxD Transfer clock SCIF Demodulation unit IrDA RxD1 Modulation unit TxD1 RxD Switching IrDA/SCIF Legend SCIF: Serial communication interface with FIFO Figure 17.1 Block Diagram of IrDA Rev. 5.00, 09/03, page 556 of 760 Figures 17.2 to 17.4 show the IrDA I/O port pins. SCIF pin I/O and data control is performed by bits 7 to 4 of SCPCR and bits 3 and 2 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR). Reset R D SCP3MD0 Q C PCRW Reset R Q D SCP3MD1 C PCRW Reset SCPT[3]/SCK1 R Q D SCP3DT1 C PDRW Output enable Serial clock output Clock input enable Internal data bus IrDA PDRR* Serial clock input Legend PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK1 pin, the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP3MD1 bit in SCPCR to 1 (see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)). Figure 17.2 SCPT[3]/SCK1 Pin Rev. 5.00, 09/03, page 557 of 760 Reset R D SCP2MD0 Q C PCRW Reset R Q D SCP2MD1 C PCRW Reset SCPT[2]/TxD1 R Q D SCP2DT1 C PDRW Output enable Serial transfer output Legend PCRW: SCPCR write PDRW: SCPDR write Internal data bus IrDA Figure 17.3 SCPT[2]/TxD1 Pin Rev. 5.00, 09/03, page 558 of 760 IrDA SCPT[2]/RxD1 Serial receive data Internal data bus PDRR* Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCPT[2]/RxD1 Pin 17.1.3 Pin Configuration The IrDA has the serial pins summarized in table 17.1. Table 17.1 IrDA Pins Pin Name Serial clock pin Receive data pin Transmit data pin Signal Name SCK1 RxD1 TxD1 I/O I/O Input Output Function Clock I/O Receive data input Transmit data output Note: Clock input from the serial clock pin cannot be set in IrDA mode. Rev. 5.00, 09/03, page 559 of 760 17.1.4 Register Configuration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, specify the data format and a bit rate, and control the transmit and receive units. Table 17.2 IrDA Registers Register Name Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit FIFO data register 1 Serial status register 1 Receive FIFO data register 1 FIFO control register 1 FIFO data count register 1 Abbreviation SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCSSR1 SCFRDR1 SCFCR1 SCFDR1 R/W R/W R/W R/W W 1 Initial Value H'00 H'FF H'00 -- Address Access Size H'04000140 8 bits 2 (H'A4000140)* H'04000142 8 bits 2 (H'A4000142)* H'04000144 8 bits 2 (H'A4000144)* H'04000146 8 bits 2 (H'A4000146)* H'04000148 16 bits 2 (H'A4000148)* H'0400014A 8 bits 2 (H'A400014A)* H'0400014C 8 bits 2 (H'A400014C)* H'0400014E 16 bits 2 (H'A400014E)* R/(W)* H'0060 R R/W R Undefined H'00 H'0000 Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 560 of 760 17.2 Register Description Specifications of the registers in the IrDA are the same as those in the SCIF except for the serial mode register described below. Therefore, refer to section 16, Serial Communication Interface with FIFO (SCIF), for details of these registers. 17.2.1 Serial Mode Register (SCSMR) Bit: Initial value: R/W: 7 IRMOD 0 R/W 6 ICK3 0 R/W 5 ICK2 0 R/W 4 ICK1 0 R/W 3 ICK0 0 R/W 2 PSEL 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCSMR is an 8-bit register that selects IrDA or SCIF mode, specifies the SCIF serial communication format, selects the IrDA output pulse width, and selects the baud rate generator clock source. This module operates as IrDA when the IRMOD bit is set to 1. At this time, bits 3 to 6 are fixed at 0. This register functions in the same way as the SCSMR register in the SCIF when the IRMOD bit is cleared to 0; therefore, this module can also operate as an SCIF. SCSMR is initialized to H'00 by a power-on reset or manual reset, when the module is stopped by the module standby function, and in standby mode. Bit 7--IrDA Mode (IRMOD): Selects whether this module operates as an IrDA serial communication interface or as an SCIF. Bit 7: IRMOD 0 1* Description Operates as an SCIF Operates as an IrDA (Initial value) Note: * Do not set the CKE1 bit in the serial control register (SCSCRT) to 1 if the IRMCD bit is set to 1. Rev. 5.00, 09/03, page 561 of 760 Bits 6 to 3--Ir Clock Select Bits (ICK3 to ICK0) Bit 2--Output Pulse Width Select (PSEL): PSEL selects an IrDA output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. The Ir clock select bits should be set properly to fix the output pulse width at 3/16 of the bit length for 115 kbps by setting the PSEL bit to 1. Bit 6 ICK3 ICK3 Don't care Bit 5 ICK2 ICK2 Don't care Bit 4 ICK1 ICK1 Don't care Bit 3 ICK0 ICK0 Don't care Bit 2 PSEL 1 0 Pulse width: 3/16 of bit length Description Pulse width: 3/16 of 115 kbps bit length It is necessary to generate a fixed clock pulse, IRCLK, by dividing the P clock by 1/2N + 2 (with the value of N determined by the setting of ICK3-ICK0). Example: P clock: 14.7456 MHz IRCLK: 921.6 kHz (fixed) N: Setting of ICK3-ICK0 (0 N 15) N P 2XIRCLK -17 Accordingly, N is 7. Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): Select the internal baud rate generator clock source. P, P/4, P/16, or P/64 can be selected by setting the CKS1 and CKS0 bits. Refer to section 14.2.9, Bit Rate Register (SCBRR), for the relationship between the clock source, the bit rate register set value, and the baud rate. Bit 1: CKS1 0 0 1 1 Bit 0: CKS0 0 1 0 1 Description P clock P/4 clock P/16 P/64 (Initial value) Note: P: Peripheral clock Rev. 5.00, 09/03, page 562 of 760 17.3 Operation Description The IrDA module can perform infrared communication conforming to IrDA 1.0 by connecting infrared transmit/receive units. The serial communication interface unit includes a 16-stage FIFO buffer in the transmit unit and the receive unit, allowing CPU overhead to be reduced and continuous high-speed communication to be performed. This module also supports DMAC data transfer. The IrDA module differs from the SCIF described in section 16, Serial Communication Interface with FIFO (SCIF) in that it does not include modem control signals RTS and CTS. Refer to section 16.3, Operation, for SCIF mode operation. 17.3.1 Overview The IrDA module modifies TxD/RxD transmit/receive data waveforms to satisfy the IrDA 1.0 specification for infrared communication. In the IrDA 1.0 specification, communication is first performed at a speed of 9600 bps, and the communication speed is changed. However, the communication rate cannot be automatically changed in this module, so the communication speed should be confirmed, and the appropriate speed set for this module by software. Note: In IrDA mode, reception cannot be performed when the TE bit in the serial control register (SCSCR) is set to 1 (enabling transmission). When performing reception, clear the TE bit in SCSCR to 0. As the SH7709S's RxD1 pin is active-high in IrDA mode, a (Schmidt) inverter must be inserted when connecting an active-low IrDA module. The RxD1 pin is active-low in SCIF mode. 17.3.2 Transmitting In the case of a serial output signal (UART frame) from the SCIF, its waveforms are modified and the signal is converted into the IR frame serial output signal by the IrDA module, as shown in figure 17.5. When serial data is 0, a pulse of 3/16 the IR frame bit width is generated and output. When serial data is 1, no pulse is output. An infrared LED is driven by this signal demodulated to 3/16 width. Rev. 5.00, 09/03, page 563 of 760 17.3.3 Receiving Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as shown in figure 17.5. Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. UART frame Start bit 0 1 0 1 0 Data 0 1 1 0 1 Stop bit Transmit Receive IR frame Start bit 0 1 0 1 0 Data 0 1 1 0 1 Stop bit Bit cycle 3/16-bit cycle pulse width Figure 17.5 Transmit/Receive Operation Rev. 5.00, 09/03, page 564 of 760 Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 18.1 lists the multiplexed pins. Table 18.1 List of Multiplexed Pins Port A A A A A A A A B B B B B B B B C C C C C C C Port Function (Related Module) PTA7 input/output (port) PTA6 input/output (port) PTA5 input/output (port) PTA4 input/output (port) PTA3 input/output (port) PTA2 input/output (port) PTA1 input/output (port) PTA0 input/output (port) PTB7 input/output (port) PTB6 input/output (port) PTB5 input/output (port) PTB4 input/output (port) PTB3 input/output (port) PTB2 input/output (port) PTB1 input/output (port) PTB0 input/output (port) PTC7 input/output (port)/PINT7 input (INTC) PTC6 input/output (port)/PINT6 input (INTC) PTC5 input/output (port)/PINT5 input (INTC) PTC4 input/output (port)/PINT4 input (INTC) PTC3 input/output (port)/PINT3 input (INTC) PTC2 input/output (port)/PINT2 input (INTC) PTC1 input/output (port)/PINT1 input (INTC) Other Function (Related Module) D23 input/output (data bus) D22 input/output (data bus) D21 input/output (data bus) D20 input/output (data bus) D19 input/output (data bus) D18 input/output (data bus) D17 input/output (data bus) D16 input/output (data bus) D31 input/output (data bus) D30 input/output (data bus) D29 input/output (data bus) D28 input/output (data bus) D27 input/output (data bus) D26 input/output (data bus) D25 input/output (data bus) D24 input/output (data bus) MCS7 output (BSC) MCS6 output (BSC) MCS5 output (BSC) MCS4 output (BSC) MCS3 output (BSC) MCS2 output (BSC) MCS1 output (BSC) Rev. 5.00, 09/03, page 565 of 760 Port C D D D D D D D D E E E E E E E E F F F F F F F F G G G G G G Port Function (Related Module) PTC0 input/output (port)/PINT0 input (INTC) PTD7 input/output (port) PTD6 input (port) PTD5 input/output (port) PTD4 input (port) PTD3 input/output (port) PTD2 input/output (port) PTD1 input/output (port) PTD0 input/output (port) PTE7 input/output (port) PTE6 input/output (port) PTE5 input/output (port) PTE4 input/output (port) PTE3 input/output (port) PTE2 input/output (port) PTE1 input/output (port) PTE0 input/output (port) PTF7 input (port)/PINT15 input (INTC) PTF6 input (port)/PINT14 input (INTC) PTF5 input (port)/PINT13 input (INTC) PTF4 input (port)/PINT12 input (INTC) PTF3 input (port)/PINT11 input (INTC) PTF2 input (port)/PINT10 input (INTC) PTF1 input (port)/PINT9 input (INTC) PTF0 input (port)/PINT8 input (INTC) PTG7 input (port) PTG6 input (port) PTG5 input (port) PTG4 input (port) PTG3 input (port) PTG2 input (port) Other Function (Related Module) MCS0 output (BSC) DACK1 output (DMAC) DREQ1 input (DMAC) DACK0 output (DMAC) DREQ0 input (DMAC) WAKEUP output (WTC) RESETOUT output DRAK0 output (DMAC) DRAK1 output (DMAC) AUDSYNC output (AUD) -- CE2B output (PCMCIA) CE2A output (PCMCIA) -- RAS3U output (BSC) -- TDO output (UDI) TRST input (AUD, UDI) TMS input (UDI) TD1 input (UDI) TCK input (UDI) IRLS3 input (INTC) IRLS2 input (INTC) IRLS1 input (INTC) IRLS0 input (INTC) IOIS16 input (PCMCIA) ASEMD0 input (AUD, UDI) ASEBRKAK output (AUD) CKIO2 output (CPG) AUDATA3 output (AUD) AUDATA2 output (AUD) Rev. 5.00, 09/03, page 566 of 760 Port G G H H H H H H H H J J J J J J J J K K K K K K K K L L L Port Function (Related Module) PTG1 input (port) PTG0 input (port) PTH7 input/output (port) PTH6 input (port) PTH5 input (port) PTH4 input (port)/IRQ4 input (INTC) PTH3 input (port)/IRQ3 input (INTC) PTH2 input (port)/IRQ2 input (INTC) PTH1 input (port)/IRQ1 input (INTC) PTH0 input (port)/IRQ0 input (INTC) PTJ7 input/output (port) PTJ6 input/output (port) PTJ5 input/output (port) PTJ4 input/output (port) PTJ3 input/output (port) PTJ2 input/output (port) PTJ1 input/output (port) PTJ0 input/output (port) PTK7 input/output (port) PTK6 input/output (port) PTK5 input/output (port) PTK4 input/output (port) PTK3 input/output (port) PTK2 input/output (port) PTK1 input/output (port) PTK0 input/output (port) PTL7 input (port) PTL6 input (port) PTL5 input (port) Other Function (Related Module) AUDATA1 output (AUD) AUDATA0 output (AUD) TCLK input/output (TMU) AUDCK input (AUD) ADTRG input (ADC) IRQ4 input (INTC) IRQ3 input (INTC) IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC) STATUS1 output (CPG) STATUS0 output (CPG) -- -- CASU output (BSC) CASL output (BSC) -- RAS3L output (BSC) WE3 output (BSC)/DQMUU output (BSC)/ICIOWR output (BSC) WE2 output (BSC)/DQMUL output (BSC)/ICIORD output (BSC) CKE output (BSC) BS output (BSC) CS5 output (BSC)/CE1A output (BSC) CS4 output (BSC) CS3 output (BSC) CS2 output (BSC) AN7 input (ADC)/DA0 output (DAC) AN6 input (ADC)/DA1 output (DAC) AN5 input (ADC) Rev. 5.00, 09/03, page 567 of 760 Port L L L L L SCPT SCPT SCPT SCPT SCPT SCPT SCPT SCPT Note: Port Function (Related Module) PTL4 input (port) PTL3 input (port) PTL2 input (port) PTL1 input (port) PTL0 input (port) SCPT7 input (port)/IRQ5 input (INTC) SCPT6 input/output (port) SCPT5 input/output (port) SCPT4 input (port) SCPT4 output (port) SCPT3 input/output (port) SCPT2 input (port) SCPT2 output (port) SCPT1 input/output (port) SCPT0 input (port) SCPT0 output (port) Other Function (Related Module) AN4 input (ADC) AN3 input (ADC) AN2 input (ADC) AN1 input (ADC) AN0 input (ADC) CTS2 input (UART ch 3)/IRQ5 input (INTC) RTS2 output (UART ch 3) SCK2 input/output (UART ch 3) RxD2 input (UART ch 3) TxD2 output (UART ch 3) SCK1 input/output (UART ch 2) RxD1 input (UART ch 2) TxD1 output (UART ch 2) SCK0 input/output (UART ch 1) RxD0 input (UART ch 1) TxD0 output (UART ch 1) SCPT0, SCPT2, and SCPT4 have the same data register to be accessed although they have different input pins and output pins. Rev. 5.00, 09/03, page 568 of 760 18.2 Register Configuration Table 18.2 summarizes the registers of the pin function controller. Table 18.2 Pin Function Controller Registers Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port J control register Port K control register Port L control register SC port control register Abbreviation PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PLCR SCPCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'AAAA H'AA8A H'AAAA/H'2AA8 H'AAAA/H'00AA H'AAAA/H'A200 H'AAAA/H'8AAA H'0000 H'0000 H'0000 H'A888 Address H'04000100 (H'A4000100)* H'04000102 (H'A4000102)* H'04000104 (H'A4000104)* H'04000106 (H'A4000106)* H'04000108 (H'A4000108)* H'0400010A (H'A400010A)* H'0400010C (H'A400010C)* H'0400010E (H'A400010E)* H'04000110 (H'A4000110)* H'04000112 (H'A4000112)* H'04000114 (H'A4000114)* H'04000116 (H'A4000116)* Access Size 16 16 16 16 16 16 16 16 16 16 16 16 Notes: 1. The initial value of the port E, F, G, and H control registers depends on the state of the ASEMD0 pin. If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. See section 22, User Debugging Interface (UDI), for more information on the UDI. 2. These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 569 of 760 18.3 18.3.1 Register Descriptions Port A Control Register (PACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA7 PA7 PA6 PA6 PA5 PA5 PA4 PA4 PA3 PA3 PA2 PA2 PA1 PA1 PA0 PA0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port A control register (PACR) is a 16-bit readable/writable register that selects the pin functions. PACR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PA7 Mode 1 and 0 (PA7MD1, PA7MD0) Bits 13 and 12--PA6 Mode 1 and 0 (PA6MD1, PA6MD0) Bits 11 and 10--PA5 Mode 1 and 0 (PA5MD1, PA5MD0) Bits 9 and 8--PA4 Mode 1 and 0 (PA4MD1, PA4MD0) Bits 7 and 6--PA3 Mode 1 and 0 (PA3MD1, PA3MD0) Bits 5 and 4--PA2 Mode 1 and 0 (PA2MD1, PA2MD0) Bits 3 and 2--PA1 Mode 1 and 0 (PA1MD1, PA1MD0) Bits 1 and 0--PA0 Mode 1 and 0 (PA0MD1, PA0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PAnMD1 0 0 1 1 Bit 2n PAnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00, 09/03, page 570 of 760 18.3.2 Port B Control Register (PBCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB7 PB7 PB6 PB6 PB5 PB5 PB4 PB4 PB3 PB3 PB2 PB2 PB1 PB1 PB0 PB0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port B control register (PBCR) is a 16-bit readable/writable register that selects the pin functions. PBCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PB7 Mode 1 and 0 (PB7MD1, PB7MD0) Bits 13 and 12--PB6 Mode 1 and 0 (PB6MD1, PB6MD0) Bits 11 and 10--PB5 Mode 1 and 0 (PB5MD1, PB5MD0) Bits 9 and 8--PB4 Mode 1 and 0 (PB4MD1, PB4MD0) Bits 7 and 6--PB3 Mode 1 and 0 (PB3MD1, PB3MD0) Bits 5 and 4--PB2 Mode 1 and 0 (PB2MD1, PB2MD0) Bits 3 and 2--PB1 Mode 1 and 0 (PB1MD1, PB1MD0) Bits 1 and 0--PB0 Mode 1 and 0 (PB0MD1, PB0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PBnMD1 0 0 1 1 Bit 2n PBnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00, 09/03, page 571 of 760 18.3.3 Port C Control Register (PCCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC7 PC7 PC6 PC6 PC5 PC5 PC4 PC4 PC3 PC3 PC2 PC2 PC1 PC1 PC0 PC0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port C control register (PCCR) is a 16-bit readable/writable register that selects the pin functions. PCCR is initialized to H'AAAA by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PC7 Mode 1 and 0 (PC7MD1, PC7MD0) Bits 13 and 12--PB6 Mode 1 and 0 (PC6MD1, PC6MD0) Bits 11 and 10--PC5 Mode 1 and 0 (PC5MD1, PC5MD0) Bits 9 and 8--PC4 Mode 1 and 0 (PC4MD1, PC4MD0) Bits 7 and 6--PC3 Mode 1 and 0 (PC3MD1, PC3MD0) Bits 5 and 4--PC2 Mode 1 and 0 (PC2MD1, PC2MD0) Bits 3 and 2--PC1 Mode 1 and 0 (PC1MD1, PC1MD0) Bits 1 and 0--PC0 Mode 1 and 0 (PC0MD1, PC0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PCnMD1 0 0 1 1 Bit 2n PCnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00, 09/03, page 572 of 760 18.3.4 Port D Control Register (PDCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD7 PD7 PD6 PD6 PD5 PD5 PD4 PD4 PD3 PD3 PD2 PD2 PD1 PD1 PD0 PD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port D control register (PDCR) is a 16-bit readable/writable register that selects the pin functions. PDCR is initialized to H'AA8A by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PD7 Mode 1 and 0 (PD7MD1, PD7MD0) Bits 11 and 10--PD5 Mode 1 and 0 (PD5MD1, PD5MD0) Bits 7 and 6--PD3 Mode 1 and 0 (PD3MD1, PD3MD0) Bits 5 and 4--PD2 Mode 1 and 0 (PD2MD1, PD2MD0) Bits 3 and 2--PD1 Mode 1 and 0 (PD1MD1, PD1MD0) Bits 1 and 0--PD0 Mode 1 and 0 (PD0MD1, PD0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PDnMD1 0 0 1 1 Bit 2n PDnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 3, 5, 7) (Initial value) (n = 0, 1, 3, 5, 7) (Initial value) (n = 2) Bits 13 and 12--PD6 Mode 1 and 0 (PD6MD1, PD6MD0) Bits 9 and 8--PD4 Mode 1 and 0 (PD4MD1, PD4MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PDnMD1 0 0 1 1 Bit 2n PDnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 4, 6) (Initial value) Rev. 5.00, 09/03, page 573 of 760 18.3.5 Port E Control Register (PECR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE7 PE7 PE6 PE6 PE5 PE5 PE4 PE4 PE3 PE3 PE2 PE2 PE1 PE1 PE0 PE0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the pin functions. PECR is initialized to H'AAAA (ASEMD0 = 1) or H'2AA8 (ASEMD0 = 0) by a power-on reset, but is not initialized by a manual reset, in software standby mode, or in sleep mode. Bits 15 and 14--PE7 Mode 1 and 0 (PE7MD1, PE7MD0) Bits 13 and 12--PE6 Mode 1 and 0 (PE6MD1, PE6MD0) Bits 11 and 10--PE5 Mode 1 and 0 (PE5MD1, PE5MD0) Bits 9 and 8--PE4 Mode 1 and 0 (PE4MD1, PE4MD0) Bits 7 and 6--PE3 Mode 1 and 0 (PE3MD1, PE3MD0) Bits 5 and 4--PE2 Mode 1 and 0 (PE2MD1, PE2MD0) Bits 3 and 2--PE1 Mode 1 and 0 (PE1MD1, PE1MD0) Bits 1 and 0--PE0 Mode 1 and 0 (PE0MD1, PE0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PEnMD1 0 0 1 1 Bit 2n PEnMD0 0 1 0 1 Pin Function Reserved (n = 0, 7) (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0, 7) Bit (2n + 1) PEnMD1 0 0 1 1 Bit 2n PEnMD0 0 1 0 1 Pin Function Other function (n = 2, 4, 5) (see table 18.1), Reserved (n = 1, 3, 6) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 1 to 6) (Initial value) (Initial value) (ASEMD0 = 1) (Initial value) (ASEMD0 = 0) Rev. 5.00, 09/03, page 574 of 760 18.3.6 Port F Control Register (PFCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF7 PF7 PF6 PF6 PF5 PF5 PF4 PF4 PF3 PF3 PF2 PF2 PF1 PF1 PF0 PF0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port F control register (PFCR) is a 16-bit readable/writable register that selects the pin functions. PFCR is initialized to H'AAAA (ASEMD0 = 1) or H'00AA (ASEMD0 = 0) by a poweron reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PF7 Mode 1 and 0 (PF7MD1, PF7MD0) Bits 13 and 12--PF6 Mode 1 and 0 (PF6MD1, PF6MD0) Bits 11 and 10--PF5 Mode 1 and 0 (PF5MD1, PF5MD0) Bits 9 and 8--PF4 Mode 1 and 0 (PF4MD1, PF4MD0) Bits 7 and 6--PF3 Mode 1 and 0 (PF3MD1, PF3MD0) Bits 5 and 4--PF2 Mode 1 and 0 (PF2MD1, PF2MD0) Bits 3 and 2--PF1 Mode 1 and 0 (PF1MD1, PF1MD0) Bits 1 and 0--PF0 Mode 1 and 0 (PF0MD1, PF0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PFnMD1 0 0 1 1 Bit 2n PFnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 4 to 7) Bit (2n + 1) PFnMD1 0 0 1 1 Bit 2n PFnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 3) (Initial value) (Initial value) (ASEMD0 = 1) (Initial value) (ASEMD0 = 0) Rev. 5.00, 09/03, page 575 of 760 18.3.7 Port G Control Register (PGCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG7 PG7 PG6 PG6 PG5 PG5 PG4 PG4 PG3 PG3 PG2 PG2 PG1 PG1 PG0 PG0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1/0 0 1 0 1/0 0 1/0 0 1/0 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port G control register (PGCR) is a 16-bit readable/writable register that selects the pin functions. PGCR is initialized to H'AAAA (ASEMD0 = 1) or H'A200 (ASEMD0 = 0) by a poweron reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PG7 Mode 1 and 0 (PG7MD1, PG7MD0) Bits 13 and 12--PG6 Mode 1 and 0 (PG6MD1, PG6MD0) Bits 11 and 10--PG5 Mode 1 and 0 (PG5MD1, PG5MD0) Bits 9 and 8--PG4 Mode 1 and 0 (PG4MD1, PG4MD0) Bits 7 and 6--PG3 Mode 1 and 0 (PG3MD1, PG3MD0) Bits 5 and 4--PG2 Mode 1 and 0 (PG2MD1, PG2MD0) Bits 3 and 2--PG1 Mode 1 and 0 (PG1MD1, PG1MD0) Bits 1 and 0--PG0 Mode 1 and 0 (PG0MD1, PG0MD0) These bits select the pin functions and perform input pull-up MOS control. Rev. 5.00, 09/03, page 576 of 760 Bit (2n + 1) PGnMD1 0 0 1 1 Bit 2n PGnMD0 0 1 0 1 Pin Function Other function (n = 1-3, 5) (see table 18.1) (Initial value) (ASEMD0 = 0) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 1 to 3, 5) (Initial value) (ASEMD0 = 1) Bit (2n + 1) PGnMD1 0 0 1 1 Bit 2n PGnMD0 0 1 0 1 Pin Function Other function (n = 4, 6, 7) (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 4, 6, 7) (Initial value)* Note: * When n = 6, ASEMD0/PTG6 functions as ASEMD0 input while the reset signal is asserted, and as PTG6 input immediately after the reset signal is nagated. Bit 3 PG1MD1* 0 0 1 1 Bit 0 PG0MD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) ASEMD0 = 1 (Initial value) ASEMD0 = 0 Note: * Controlled by PG1MD1 (bit 3), not PG0MD1 (bit 1). 18.3.8 Port H Control Register (PHCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PH7 PH7 PH6 PH6 PH5 PH5 PH4 PH4 PH3 PH3 PH2 PH2 PH1 PH1 PH0 PH0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port H control register (PHCR) is a 16-bit readable/writable register that selects the pin functions. PHCR is initialized to H'AAAA (ASEMD0 = 1) or H'8AAA (ASEMD0 = 0) by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Rev. 5.00, 09/03, page 577 of 760 Bits 15 and 14--PH7 Mode 1, 0 (PH7MD1, PH7MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 15 PH7MD1 0 0 1 1 Bit 14 PH7MD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Bits 13 and 12--PH6 Mode 1 and 0 (PH6MD1, PH6MD0) Bits 11 and 10--PH5 Mode 1 and 0 (PH5MD1, PH5MD0) Bits 9 and 8--PH4 Mode 1 and 0 (PH4MD1, PH4MD0) Bits 7 and 6--PH3 Mode 1 and 0 (PH3MD1, PH3MD0) Bits 5 and 4--PH2 Mode 1 and 0 (PH2MD1, PH2MD0) Bits 3 and 2--PH1 Mode 1 and 0 (PH1MD1, PH1MD0) Bits 1 and 0--PH0 Mode 1 and 0 (PH0MD1, PH0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit 13 PH6MD1 0 0 1 1 Bit 12 PH6MD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) (ASEMD0 = 1) (Initial value) (ASEMD0 = 0) Bit (2n + 1) PHnMD1 0 0 1 1 Bit 2n PHnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 5) (Initial value) Rev. 5.00, 09/03, page 578 of 760 18.3.9 Port J Control Register (PJCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ7 PJ7 PJ6 PJ6 PJ5 PJ5 PJ4 PJ4 PJ3 PJ3 PJ2 PJ2 PJ1 PJ1 PJ0 PJ0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port J control register (PJCR) is a 16-bit readable/writable register that selects the pin functions. PJCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PJ7 Mode 1 and 0 (PJ7MD1, PJ7MD0) Bits 13 and 12--PJ6 Mode 1 and 0 (PJ6MD1, PJ6MD0) Bits 11 and 10--PJ5 Mode 1 and 0 (PJ5MD1, PJ5MD0) Bits 9 and 8--PJ4 Mode 1 and 0 (PJ4MD1, PJ4MD0) Bits 7 and 6--PJ3 Mode 1 and 0 (PJ3MD1, PJ3MD0) Bits 5 and 4--PJ2 Mode 1 and 0 (PJ2MD1, PJ2MD0) Bits 3 and 2--PJ1 Mode 1 and 0 (PJ1MD1, PJ1MD0) Bits 1 and 0--PJ0 Mode 1 and 0 (PJ0MD1, PJ0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PJnMD1 0 0 1 1 Bit 2n PJnMD0 0 1 0 1 Pin Function Other function (n = 0, 2, 3, 6, 7) (see table 18.1), Reserved (n = 1, 4, 5) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00, 09/03, page 579 of 760 18.3.10 Port K Control Register (PKCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PK7 PK7 PK6 PK6 PK5 PK5 PK4 PK4 PK3 PK3 PK2 PK2 PK1 PK1 PK0 PK0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port K control register (PKCR) is a 16-bit readable/writable register that selects the pin functions. PKCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PK7 Mode 1 and 0 (PK7MD1, PK7MD0) Bits 13 and 12--PK6 Mode 1 and 0 (PK6MD1, PK6MD0) Bits 11 and 10--PK5 Mode 1 and 0 (PK5MD1, PK5MD0) Bits 9 and 8--PK4 Mode 1 and 0 (PK4MD1, PK4MD0) Bits 7 and 6--PK3 Mode 1 and 0 (PK3MD1, PK3MD0) Bits 5 and 4--PK2 Mode 1 and 0 (PK2MD1, PK2MD0) Bits 3 and 2--PK1 Mode 1 and 0 (PK1MD1, PK1MD0) Bits 1 and 0--PK0 Mode 1 and 0 (PK0MD1, PK0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PKnMD1 0 0 1 1 Bit 2n PKnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00, 09/03, page 580 of 760 18.3.11 Port L Control Register (PLCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL7 PL7 PL6 PL6 PL5 PL5 PL4 PL4 PL3 PL3 PL2 PL2 PL1 PL1 PL0 PL0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port L control register (PLCR) is a 16-bit readable/writable register that selects the pin functions. PLCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bits 15 and 14--PL7 Mode 1 and 0 (PL7MD1, PL7MD0) Bits 13 and 12--PL6 Mode 1 and 0 (PL6MD1, PL6MD0) Bits 11 and 10--PL5 Mode 1 and 0 (PL5MD1, PL5MD0) Bits 9 and 8--PL4 Mode 1 and 0 (PL4MD1, PL4MD0) Bits 7 and 6--PL3 Mode 1 and 0 (PL3MD1, PL3MD0) Bits 5 and 4--PL2 Mode 1 and 0 (PL2MD1, PL2MD0) Bits 3 and 2--PL1 Mode 1 and 0 (PL1MD1, PL1MD0) Bits 1 and 0--PL0 Mode 1 and 0 (PL0MD1, PL0MD0) These bits select the pin functions and perform input pull-up MOS control. Bit (2n + 1) PLnMD1 0 0 1 1 Bit 2n PLnMD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (n = 0 to 7) (Initial value) When the DA0 and DA1 pins are used as the D/A converter outputs or when PTL7 and PTL6 are used in the "other function" state, PLCR should by kept at its initial value. Rev. 5.00, 09/03, page 581 of 760 18.3.12 SC Port Control Register (SCPCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The SC port control register (SCPCR) is a 16-bit readable/writable register that selects the pin functions. The setting of SCPCR is valid only when transmit/receive operations are disabled in the SCSCR register. SCPCR is initialized to H'A888 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. When the TE bit in SCSCR is set to 1, the "other function" output state has a higher priority than the SCPCR setting for the TxD[2:0] pins. When the RE bit in SCSCR is set to 1, the input state has a higher priority than the SCPCR setting for the RxD[2:0] pins. Bits 15 and 14--SCP7 Mode 1 and 0 (SCP7MD1, SCP7MD0): These bits select the pin function and perform input pull-up MOS control. Bit 15 SCP7MD1 0 0 1 1 Bit 14 SCP7MD0 0 1 0 1 Pin Function Other function (see table 18.1) Reserved Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Bits 13, 12--SCP6 Mode 1, 0 (SCP6MD1, SCP6MD0): These bits select the pin function and perform input pull-up MOS control. Bit 13 SCP6MD1 0 0 1 1 Bit 12 SCP6MD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Rev. 5.00, 09/03, page 582 of 760 Bits 11 and 10--SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 11 SCP5MD1 0 0 1 1 Bit 10 SCP5MD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Bits 9 and 8--SCP4 Mode 1 and 0 (SCP4MD1, SCP4MD0): These bits select the pin function and perform input pull-up MOS control. Bit 9 SCP4MD1 0 0 1 1 Bit 8 SCP4MD0 0 1 0 1 Pin Function Transmit data output 2 (TxD2) Receive data input 2 (RxD2) General output (SCPT[4] output pin) Receive data input 2 (RxD2) SCPT[4] input pin pull-up (input pin) Transmit data output 2 (TxD2) General input (SCPT[4] input pin) Transmit data output 2 (TxD2) (Initial value) Note: There is no SCPT[4] simultaneous I/O combination because one bit (SCP4DT) is accessed using two pins, TxD2 and RxD2. When port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD2 pin is in the output state. When the TE bit is cleared to 0, the TxD2 pin goes to the highimpedance state. Bits 7 and 6--SCP3 Mode 1 and 0 (SCP3MD1, SCP3MD0): These bits select the pin function and perform input pull-up MOS control. Bit 7 SCP3MD1 0 0 1 1 Bit 6 SCP3MD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Rev. 5.00, 09/03, page 583 of 760 Bits 5 and 4--SCP2 Mode 1 and 0 (SCP2MD1, SCP2MD0): These bits select the pin function and perform input pull-up MOS control. Bit 5 SCP2MD1 0 0 1 1 Bit 4 SCP2MD0 0 1 0 1 Pin Function Transmit data output 1 (TxD1) Receive data input 1 (RxD1) General output (SCPT[2] output pin) Receive data input 1 (RxD1) SCPT[2] input pin pull-up (input pin) Transmit data output 1 (TxD1) General input (SCPT[2] input pin) Transmit data output 1 (TxD1) (Initial value) Note: There is no SCPT[2] simultaneous I/O combination because one bit (SCP2DT) is accessed using two pins, TxD1 and RxD1. When port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD1 pin is in the output state. When the TE bit is cleared to 0, the TxD1 pin goes to the highimpedance state. Bits 3 and 2--SCP1 Mode 1 and 0 (SCP1MD1, SCP1MD0): These bits select the pin function and perform input pull-up MOS control. Bit 3 SCP1MD1 0 0 1 1 Bit 2 SCP1MD0 0 1 0 1 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) Port input (Pull-up MOS: off) (Initial value) Rev. 5.00, 09/03, page 584 of 760 Bits 1 and 0--SCP0 Mode 1 and 0 (SCP0MD1, SCP0MD0): These bits select the pin function and perform input pull-up MOS control. Bit 1 SCP0MD1 0 0 1 1 Bit 0 SCP0MD0 0 1 0 1 Pin Function Transmit data output 0 (TxD0) Receive data input 0 (RxD0) General output (SCPT[0] output pin) Receive data input 0 (RxD0) SCPT[0] input pin pull-up (input pin) Transmit data output 0 (TxD0) General input (SCPT[0] input pin) Transmit data output 0 (TxD0) (Initial value) Note: There is no SCPT[0] simultaneous I/O combination because one bit (SCP0DT) is accessed using two pins, TxD0 and RxD0. When port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD0 pin is in the output state. When the TE bit is cleared to 0, the TxD0 pin goes to the highimpedance state. Rev. 5.00, 09/03, page 585 of 760 Rev. 5.00, 09/03, page 586 of 760 Section 19 I/O Ports 19.1 Overview The SH7709S has twelve 8-bit ports (ports A to L and SC). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins. 19.2 Port A Port A is an 8-bit input/output port with the pin configuration shown in figure 19.1. Each pin has an input pull-up MOS, which is controlled by the port A control register (PACR) in the PFC. PTA7 (input/output) / D23 (input/output) PTA6 (input/output) / D22 (input/output) PTA5 (input/output) / D21 (input/output) Port A PTA4 (input/output) / D20 (input/output) PTA3 (input/output) / D19 (input/output) PTA2 (input/output) / D18 (input/output) PTA1 (input/output) / D17 (input/output) PTA0 (input/output) / D16 (input/output) Figure 19.1 Port A 19.2.1 Register Description Table 19.1 summarizes the port A register. Table 19.1 Port A Register Name Port A data register Abbreviation PADR R/W R/W Initial Value H'00 Address Access Size H'04000120 8 (H'A4000120)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 587 of 760 19.2.2 Port A Data Register (PADR) Bit: Initial value: R/W: 7 PA7DT 0 R/W 6 PA6DT 0 R/W 5 PA5DT 0 R/W 4 PA4DT 0 R/W 3 PA3DT 0 R/W 2 PA2DT 0 R/W 1 PA1DT 0 R/W 0 PA0DT 0 R/W The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.2 shows the function of PADR. PADR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Table 19.2 Port A Data Register (PADR) Read/Write Operations PAnMD1 0 PAnMD0 0 1 1 0 1 Pin State Other function (See table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PADR value PADR value Pin state Pin state Write Value is written to PADR, but does not affect pin state Write value is output from pin Value is written to PADR, but does not affect pin state Value is written to PADR, but does not affect pin state (n = 7 to 0) Rev. 5.00, 09/03, page 588 of 760 19.3 Port B Port B is an 8-bit input/output port with the pin configuration shown in figure 19.2. Each pin has an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC. PTB7 (input/output) / D31 (input/output) PTB6 (input/output) / D30 (input/output) PTB5 (input/output) / D29 (input/output) Port B PTB4 (input/output) / D28 (input/output) PTB3 (input/output) / D27 (input/output) PTB2 (input/output) / D26 (input/output) PTB1 (input/output) / D25 (input/output) PTB0 (input/output) / D24 (input/output) Figure 19.2 Port B 19.3.1 Register Description Table 19.3 summarizes the port B register. Table 19.3 Port B Register Name Port B data register Abbreviation PBDR R/W R/W Initial Value H'00 Address H'04000122 (H'A4000122)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 589 of 760 19.3.2 Port B Data Register (PBDR) Bit: Initial value: R/W: 7 PB7DT 0 R/W 6 PB6DT 0 R/W 5 PB5DT 0 R/W 4 PB4DT 0 R/W 3 PB3DT 0 R/W 2 PB2DT 0 R/W 1 PB1DT 0 R/W 0 PB0DT 0 R/W The port B data register (PBDR) is an 8-bit readable/writable register that stores data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.4 shows the function of PBDR. PBDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Table 19.4 Port B Data Register (PBDR) Read/Write Operations PBnMD1 0 PBnMD0 0 1 1 0 1 Pin State Other function (See table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PBDR value PBDR value Pin state Pin state Write Value is written to PBDR, but does not affect pin state Write value is output from pin Value is written to PBDR, but does not affect pin state Value is written to PBDR, but does not affect pin state (n = 7 to 0) Rev. 5.00, 09/03, page 590 of 760 19.4 Port C Port C is an 8-bit input/output port with the pin configuration shown in figure 19.3. Each pin has an input pull-up MOS, which is controlled by the port C control register (PCCR) in the PFC. PTC7 (input/output) / PINT7 (input) / MSC7 (output) PTC6 (input/output) / PINT6 (input) / MSC6 (output) PTC5 (input/output) / PINT5 (input) / MSC5 (output) Port C PTC4 (input/output) / PINT4 (input) / MSC4 (output) PTC3 (input/output) / PINT3 (input) / MSC3 (output) PTC2 (input/output) / PINT2 (input) / MSC2 (output) PTC1 (input/output) / PINT1 (input) / MSC1 (output) PTC0 (input/output) / PINT0 (input) / MSC0 (output) Figure 19.3 Port C 19.4.1 Register Description Table 19.5 summarizes the port C register. Table 19.5 Port C Register Name Port C data register Abbreviation PCDR R/W R/W Initial Value H'00 Address H'04000124 (H'A4000124)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 591 of 760 19.4.2 Port C Data Register (PCDR) Bit: Initial value: R/W: 7 PC7DT 0 R/W 6 PC6DT 0 R/W 5 PC5DT 0 R/W 4 PC4DT 0 R/W 3 PC3DT 0 R/W 2 PC2DT 0 R/W 1 PC1DT 0 R/W 0 PC0DT 0 R/W The port C data register (PCDR) is an 8-bit readable/writable register that stores data for pins PTC7 to PTC0. Bits PC7DT to PC0DT correspond to pins PTC7 to PTC0. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.6 shows the function of PCDR. PCDR is initialized to H'00 by a power-on reset, after which the general input port function (pullup MOS on) is set as the initial pin function, and the corresponding pin levels are read. PCDR retains its previous value in standby mode and sleep mode, and in a manual reset. Table 19.6 Port C Data Register (PCDR) Read/Write Operations PCnMD1 0 PCnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PCDR value PCDR value Pin state Pin state Write Value is written to PCDR, but does not affect pin state Write value is output from pin Value is written to PCDR, but does not affect pin state Value is written to PCDR, but does not affect pin state (n = 7 to 0) Rev. 5.00, 09/03, page 592 of 760 19.5 Port D Port D comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 19.4. Each pin has an input pull-up MOS, which is controlled by the port D control register (PDCR) in the PFC. PTD7 (input/output) / DACK1 (output) PTD6 (input) / DREQ1 (input) PTD5 (input/output) / DACK0 (output) Port D PTD4 (input) / DREQ0 (input) PTD3 (input/output) / WAKEUP (output) PTD2 (input/output) / RESETOUT (output) PTD1 (input/output) / DRAK0 (output) PTD0 (input/output) / DRAK1 (output) Figure 19.4 Port D 19.5.1 Register Description Table 19.7 summarizes the port D register. Table 19.7 Port D Register Name Port D data register Abbreviation PDDR R/W R/W or R Initial Value B'0*0*0000 Address Access Size H'04000126 8 1 (H'A4000126)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * Means no value. *1 When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 593 of 760 19.5.2 Port D Data Register (PDDR) Bit: Initial value: R/W: 7 PD7DT 0 R/W 6 PD6DT * R 5 PD5DT 0 R/W 4 PD4DT * R 3 PD3DT 0 R/W 2 PD2DT 0 R/W 1 PD1DT 0 R/W 0 PD0DT 0 R/W Note: * Undefined The port D data register (PDDR) is a 6-bit readable/writable and 2-bit read-only register that stores data for pins PTD7 to PTD0. Bits PD7DT to PD0DT correspond to pins PTD7 to PTD0. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.8 shows the function of PDDR. PDDR is initialized to B'0*0*0000 by a power-on reset. After initialization, the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read from bits PD7DT--PD3DT, PD1DT, and PD0DT. PDDR retains its previous value in standby mode and sleep mode, and in a manual reset. Note that the low level is read if bits 6 and 4 are read except in general-purpose input. Table 19.8 Port D Data Register (PDDR) Read/Write Operations PDnMD1 0 PDnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PDDR value PDDR value Pin state Pin state Write Value is written to PDDR, but does not affect pin state Write value is output from pin Value is written to PDDR, but does not affect pin state Value is written to PDDR, but does not affect pin state (n = 0, 1, 2, 3, 5, 7) PDnMD1 0 PDnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Reserved Input (Pull-up MOS on) Input (Pull-up MOS off) Read Low level Low level Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 4, 6) Rev. 5.00, 09/03, page 594 of 760 19.6 Port E Port E is an 8-bit input/output port with the pin configuration shown in figure 19.5. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. PTE7 (input/output) / AUDSYNC (output) PTE6 (input/output) PTE5 (input/output) / CE2B (output) Port E PTE4 (input/output) / CE2A (output) PTE3 (input/output) PTE2 (input/output) / RAS3U (output) PTE1 (input/output) PTE0 (input/output) / TDO (output) Figure 19.5 Port E 19.6.1 Register Description Table 19.9 summarizes the port E register. Table 19.9 Port E Register Name Port E data register Abbreviation PEDR R/W R/W Initial Value H'00 Address H'04000128 (H'A4000128)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 595 of 760 19.6.2 Port E Data Register (PEDR) Bit: Initial value: R/W: 7 PE7DT 0 R/W 6 PE6DT 0 R/W 5 PE5DT 0 R/W 4 PE4DT 0 R/W 3 PE3DT 0 R/W 2 PE2DT 0 R/W 1 PE1DT 0 R/W 0 PE0DT 0 R/W The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.10 shows the function of PEDR. PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pullup MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. Table 19.10 Port E Data Register (PEDR) Read/Write Operations PEnMD1 0 PEnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PEDR value PEDR value Pin state Pin state Write Value is written to PEDR, but does not affect pin state Write value is output from pin Value is written to PEDR, but does not affect pin state Value is written to PEDR, but does not affect pin state (n = 0 to 7) Rev. 5.00, 09/03, page 596 of 760 19.7 Port F Port F is an 8-bit input port with the pin configuration shown in figure 19.6. Each pin has an input pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC. PTF7 (input) / PINT15 (input) / TRST (input) PTF6 (input) / PINT14 (input) / TMS (input) PTF5 (input) / PINT13 (input) / TDI (input) Port F PTF4 (input) / PINT12 (input) / TCK (input) PTF3 (input) / PINT11 (input) / IRLS3 (input) PTF2 (input) / PINT10 (input) / IRSL2 (input) PTF1 (input) / PINT9 (input) / IRLS1 (input) PTF0 (input) / PINT8 (input) / IRLS0 (input) Figure 19.6 Port F 19.7.1 Register Description Table 19.11 summarizes the port F register. Table 19.11 Port F Register Name Port F data register Abbreviation PFDR R/W R Initial Value H'** Address Access Size H'0400012A 8 1 (H'A400012A)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * Means no value. *1 When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 597 of 760 19.7.2 Port F Data Register (PFDR) Bit: Initial value: R/W: 7 PF7DT * R 6 PF6DT * R 5 PF5DT * R 4 PF4DT * R 3 PF3DT * R 2 PF2DT * R 1 PF1DT * R 0 PF0DT * R Note: * Undefined The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.12 shows the function of PFDR. PFDR is initialized by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. Table 19.12 Port F Data Register (PFDR) Read/Write Operations PFnMD1 0 PFnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Reserved Input (Pull-up MOS on) Input (Pull-up MOS off) Read H'00 H'00 Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 0 to 7) Rev. 5.00, 09/03, page 598 of 760 19.8 Port G Port G comprises a 5-bit input/output port and 3-bit input port with the pin configuration shown in figure 19.7. Each pin has an input pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC. PTG7 (input) / IOIS16 (input) PTG6 (input) / ASEMD0 (input) PTG5 (input) / ASEBRKAK (output) Port G PTG4 (input) / CKIO2 (output) PTG3 (input) / AUDATA3 (input/output) PTG2 (input) / AUDATA2 (input/output) PTG1 (input) / AUDATA1 (input/output) PTG0 (input) / AUDATA0 (input/output) Figure 19.7 Port G 19.8.1 Register Description Table 19.13 summarizes the port G register. Table 19.13 Port G Register Name Port G data register Abbreviation PGDR R/W R/W Initial Value H'** Address Access Size H'0400012C 8 1 (H'A400012C)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * Means no value. *1 When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 599 of 760 19.8.2 Port G Data Register (PGDR) Bit: Initial value: R/W: 7 PG7DT * R 6 PG6DT * R 5 PG5DT * R 4 PG4DT * R 3 PG3DT * R 2 PG2DT * R 1 PG1DT * R 0 PG0DT * R Note: * Undefined The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general input port, if the port is read the corresponding pin level is read. Table 19.14 shows the function of PGDR. PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. Table 19.14 Port G Data Register (PGDR) Read/Write Operations PGnMD1 0 PGnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Reserved Input (Pull-up MOS on) Input (Pull-up MOS off) Read H'00 H'00 Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 0 to 7) Rev. 5.00, 09/03, page 600 of 760 19.9 Port H Port H comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 19.8. Each pin has an input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC. PTH7 (input/output) / TCLK (output) PTH6 (input) / AUDCK (input) PTH5 (input) / ADTRG (input) Port H PTH4 (input) / IRQ4 (input) PTH3 (input) / IRQ3 (input) PTH2 (input) / IRQ2 (input) PTH1 (input) / IRQ1 (input) PTH0 (input) / IRQ0 (input) Figure 19.8 Port H 19.9.1 Register Description Table 19.15 summarizes the port H register. Table 19.15 Port H Register Name Port H data register Abbreviation PHDR R/W Initial Value Address Access Size R/W or R B'0******* H'0400012E 8 1 (H'A400012E)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * Means no value. *1 When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 601 of 760 19.9.2 Port H Data Register (PHDR) Bit: Initial value: R/W: 7 PH7DT 0 R/W 6 PH6DT * R 5 PH5DT * R 4 PH4DT * R 3 PH3DT * R 2 PH2DT * R 1 PH1DT * R 0 PH0DT * R Note: * Undefined The port H data register (PHDR) is a 1-bit readable/writable and 7-bit read-only register that stores data for pins PTH7 to PTH0. Bits PH7DT to PH0DT correspond to pins PTH7 to PTH0. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.16 shows the function of PHDR. PHDR is initialized to B'0******* by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. Note that the low level is read if bits 6 to 0 are read except in general-purpose input. Table 19.16 Port H Data Register (PHDR) Read/Write Operations PHnMD1 0 PHnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PHDR value PHDR value Pin state Pin state Write Value is written to PHDR, but does not affect pin state Write value is output from pin Value is written to PHDR, but does not affect pin state Value is written to PHDR, but does not affect pin state (n = 7) PHnMD1 0 PHnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Reserved Input (Pull-up MOS on) Input (Pull-up MOS off) Read Low level Low level Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 0 to 6) Rev. 5.00, 09/03, page 602 of 760 19.10 Port J Port J is an 8-bit input/output port with the pin configuration shown in figure 19.9. Each pin has an input pull-up MOS, which is controlled by the port J control register (PJCR) in the PFC. PTJ7 (input/output) / STATUS1 (output) PTJ6 (input/output) / STATUS0 (output) PTJ5 (input/output) Port J PTJ4 (input/output) PTJ3 (input/output) / CASU (output) PTJ2 (input/output) / CASL (output) PTJ1 (input/output) PTJ0 (input/output) / RAS3L (output) Figure 19.9 Port J 19.10.1 Register Description Table 19.17 summarizes the port J register. Table 19.17 Port J Register Name Port J data register Abbreviation PJDR R/W R/W Initial Value H'00 Address H'04000130 (H'A4000130)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 603 of 760 19.10.2 Port J Data Register (PJDR) Bit: Initial value: R/W: 7 PJ7DT 0 R/W 6 PJ6DT 0 R/W 5 PJ5DT 0 R/W 4 PJ4DT 0 R/W 3 PJ3DT 0 R/W 2 PJ2DT 0 R/W 1 PJ1DT 0 R/W 0 PJ0DT 0 R/W The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7 to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.18 shows the function of PJDR. PJDR is initialized to H'00 by a power-on reset. It retains its previous value in software standby mode and sleep mode, and in a manual reset. Table 19.18 Port J Data Register (PJDR) Read/Write Operations PJnMD1 0 PJnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PJDR value PJDR value Pin state Pin state Write Value is written to PJDR, but does not affect pin state Write value is output from pin Value is written to PJDR, but does not affect pin state Value is written to PJDR, but does not affect pin state (n = 0 to 7) Rev. 5.00, 09/03, page 604 of 760 19.11 Port K Port K is an 8-bit input/output port with the pin configuration shown in figure 19.10. Each pin has an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC. PTK7 (input/output) / WE3 (output) / DQMUU (output) / ICIOWR (output) PTK6 (input/output) / WE2 (output) / DQMUL (output) / ICIORD (output) PTK5 (input/output) / CKE (output) Port K PTK4 (input/output) / BS (output) PTK3 (input/output) / CS5 (output) / CE1A (output) PTK2 (input/output) / CS4 (output) PTK1 (input/output) / CS3 (output) PTK0 (input/output) / CS2 (output) Figure 19.10 Port K 19.11.1 Register Description Table 19.19 summarizes the port K register. Table 19.19 Port K Register Name Port K data register Abbreviation PKDR R/W R/W Initial Value H'00 Address H'04000132 (H'A4000132)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 605 of 760 19.11.2 Port K Data Register (PKDR) Bit: Initial value: R/W: 7 PK7DT 0 R/W 6 PK6DT 0 R/W 5 PK5DT 0 R/W 4 PK4DT 0 R/W 3 PK3DT 0 R/W 2 PK2DT 0 R/W 1 PK1DT 0 R/W 0 PK0DT 0 R/W The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function is general output port, if the port is read, the value of the corresponding PKDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.20 shows the function of PKDR. PKDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Table 19.20 Port K Data Register (PKDR) Read/Write Operations PKnMD1 0 PKnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PKDR value PKDR value Pin state Pin state Write Value is written to PKDR, but does not affect pin state Write value is output from pin Value is written to PKDR, but does not affect pin state Value is written to PKDR, but does not affect pin state (n = 0 to 7) Rev. 5.00, 09/03, page 606 of 760 19.12 Port L Port L is an 8-bit input port with the pin configuration shown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) / DA1 (input) PTL5 (input) / AN5 (input) Port L PTL4 (input) / AN4 (input) PTL3 (input) / AN3 (input) PTL2 (input) / AN2 (input) PTL1 (input) / AN1 (input) PTL0 (input) / AN0 (input) Figure 19.11 Port L 19.12.1 Register Description Table 19.21 summarizes the port L register. Table 19.21 Port L Register Name Port L data register Abbreviation PLDR R/W R Initial Value H'00 Address H'04000134 (H'A4000134)* Access Size 8 Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 607 of 760 19.12.2 Port L Data Register (PLDR) Bit: Initial value: R/W: 7 PL7DT 0 R 6 PL6DT 0 R 5 PL5DT 0 R 4 PL4DT 0 R 3 PL3DT 0 R 2 PL2DT 0 R 1 PL1DT 0 R 0 PL0DT 0 R The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.22 shows the function of PLDR. PKDR is initialized to H'00 by power-on reset. It retains its previous value in software standby mode and sleep mode, and in a manual reset. The port L is also used as an analog pin, therefore does not have a pull-up MOS. Table 19.22 Port L Data Register (PLDR) Read/Write Operation PLnMD1 0 PLnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Reserved Input Input Read H'00 H'00 Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 0 to 7) Rev. 5.00, 09/03, page 608 of 760 19.13 SC Port The SC port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 19.12. Each pin has an input pull-up MOS, which is controlled by the SC port control register (SCPCR) in the PFC. SCPT7 (input) / CTS2 (input) / IRQ5 (input) SCPT6 (input/output) / RTS2 (output) SCPT5 (input/output) / SCK2 (input/output) SCPT4 (input) / RxD2 (input) SCPT4 (output) / TxD2 (output) SC Port SCPT3 (input/output) / SCK1 (input/output) SCPT2 (input) / RxD1 (input) SCPT2 (output) / TxD1 (output) SCPT1 (input/output) / SCK0 (input/output) SCPT0 (input) / RxD0 (input) SCPT0 (output) / TxD0 (output) Figure 19.12 SC Port 19.13.1 Register Description Table 19.23 summarizes the SC port register. Table 19.23 SC Port Register Name SC Port data register Abbreviation SCPDR R/W R/W or R Initial Value B'*0000000 Address Access Size H'04000136 8 1 (H'A4000136)* Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either access this register from the P2 area of logical space or else make an appropriate setting using the MMU so that this register is not cached. * Means no value. *1 When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 609 of 760 19.13.2 SC Port Data Register (SCPDR) Bit: Initial value: R/W: Note: * Undefined 7 * R 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT The SC port data register (SCPDR) is a 7-bit readable/writable and 1-bit read-only register that stores data for pins SCPT7 to SCPT0. Bits SCP7DT to SCP0DT correspond to pins SCPT7 to SCPT0. When the pin function is general output port, if the port is read, the value of the corresponding SCPDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 19.24 shows the function of SCPDR. SCPDR is initialized to B'*0000000 by a power-on reset. After initialization, the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read from bits SCP7DT--SCP5DT, SCP3DT, and SCP1DT. SCPDR retains its previous value in standby mode and sleep mode, and in a manual reset. Note that the low level is read if bit 7 is read except in general-purpose input. When the pin states of the RxD2 to RxD0 of the SCP4DT, SCP2DT, and SCP0DT bits in SCPDR are read while the TE and RE bits in SCSCR are not cleared to 0, the RE bit in SCSCR should be set to 1. When the RE bit is set to 1, the RxD pins become an input state and their pin states can be read prior to the SCPCR setting. Rev. 5.00, 09/03, page 610 of 760 Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 0 SCPnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read SCPDR value SCPDR value Pin state Pin state Write Value is written to SCPDR, but does not affect pin state Write value is output from pin Value is written to SCPDR, but does not affect pin state Value is written to SCPDR, but does not affect pin state (n = 0 to 6) SCPnMD1 0 SCPnMD0 0 1 1 0 1 Pin State Other function (see table 18.1) Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read Low level Low level Pin state Pin state Write Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) Ignored (no effect on pin state) (n = 7) Rev. 5.00, 09/03, page 611 of 760 Rev. 5.00, 09/03, page 612 of 760 Section 20 A/D Converter 20.1 Overview The SH7709S includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 20.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight input channels * High-speed conversion Conversion time: maximum 15 s per channel (P = 33 MHz operation) * Three conversion modes Single mode: A/D conversion on one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at the end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. Rev. 5.00, 09/03, page 613 of 760 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter. Peripheral data bus AVCC 10-bit D/A Successive approximation register ADDRC ADDRD ADDRA ADDRB ADCSR AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer - Comparator Sample-andhold circuit ADI interrupt signal A/D converter Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Control circuit + /8 /16 ADTRG Figure 20.1 Block Diagram of A/D Converter Rev. 5.00, 09/03, page 614 of 760 ADCR Bus interface Internal data bus 20.1.3 Input Pins Table 20.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply inputs for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage pin. Table 20.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVcc AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group1 analog inputs Function Analog power supply Analog ground and reference voltage Group 0 analog inputs Rev. 5.00, 09/03, page 615 of 760 20.1.4 Register Configuration Table 20.2 summarizes the A/D converter's registers. Table 20.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address Access size H'04000080 16, 8 2 (H'A4000080)* H'04000082 8 2 (H'A4000082)* H'04000084 16, 8 2 (H'A4000084)* H'04000086 8 2 (H'A4000086)* H'04000088 16, 8 2 (H'A4000088)* H'0400008A 8 2 (H'A400008A)* H'0400008C 16, 8 2 (H'A400008C)* H'0400008E 8 2 (H'A400008E)* H'04000090 8 2 (H'A4000090)* H'04000092 8 2 (H'A4000092)* 1 R/(W)* H'00 R/W H'07 Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to bit 7, to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 616 of 760 20.2 20.2.1 Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) Upper register: H Bit: Initial value: R/W: 7 AD9 0 R 6 AD8 0 R 5 AD7 0 R 4 AD6 0 R 3 AD5 0 R 2 AD4 0 R 1 AD3 0 R 0 AD2 0 R Lower register: L Bit: Initial value: R/W: n = A to D 7 AD1 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte (bits 7 to 0) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and 6). Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 20.3 indicates the pairings of analog input channels and A/D data registers. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 20.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 5.00, 09/03, page 617 of 760 20.2.2 A/D Control/Status Register (ADCSR) Bit: Initial value: R/W: 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 MULTI 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Write 0 to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF 0 Description [Clearing conditions] (1) Cleared by reading ADF while ADF = 1, then writing 0 to ADF (2) Cleared when DMAC is activated by ADI interrupt and ADDR is read 1 [Setting conditions] (1) Single mode: A/D conversion ends (2) Multi mode: A/D conversion ends on all selected channels (3) Scan mode: A/D conversion ends on all selected channels (Initial value) Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. The ADIE bit should be set while the A/D conversion stops. Bit 6: ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Rev. 5.00, 09/03, page 618 of 760 Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5: ADST 0 1 Description A/D conversion is stopped (Initial value) (1) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends (2) Multi mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends on all selected channels (3) Scan mode: A/D conversion starts and continues, cycling through the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode Bit 4--Multi Mode (MULTI): Selects single mode, multi mode or scan mode. For further information on operation in these modes, see section 20.4, Operation. Bit 4: MULTI 0 1 ADCR: Bit5: SCN Description 0 1 0 1 Multi mode Scan mode Single mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time. Bit 3:CKS 0 1 Description Conversion time = 536 states (maximum) Conversion time = 266 states (maximum) (Initial value) Rev. 5.00, 09/03, page 619 of 760 Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Channel Selection CH2 0 CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Single Mode (MULTI = 0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Multi Mode and Scan Mode (MULTI = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Rev. 5.00, 09/03, page 620 of 760 20.2.3 A/D Control Register (ADCR) Bit: 7 TRGE1 0 R/W 6 TRGE0 0 R/W 5 SCN 0 R/W 4 0 R/W 3 0 R/W 2 -- 1 R 1 -- 1 R 0 -- 1 R RESVD1 RESVD2 Initial value: R/W: ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bit 7 and 6--Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D conversion. The TRGE1 and TRGE0 bits should only be set when conversion is not in progress. Bit 7: TRGE1 0 0 1 1 Bit 6: TRGE0 0 1 0 1 Description A/D conversion does not start when an external trigger is input (Initial value) A/D conversion starts at the falling edge of an input signal from the external trigger pin (ADTRG) Bit 5--Scan Mode (SCN): Selects multi mode or scan mode when the MULTI bit is set to 1. See the description of bit 4 in section 20.2.2, A/D Control/Status Register (ADCSR). Bits 4 and 3--Reserved (RESVD1, RESVD2): These bits are always read as 0. The write value should always be 0. Bits 2 to 0--Reserved: These bits are always read as 1. The write value should always be 1. Rev. 5.00, 09/03, page 621 of 760 20.3 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the bus master. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed. Figure 20.2 shows the data flow for access to an A/D data register. See section 20.7.3, Access Size and Read Data. Upper byte read Module internal data bus CPU (H'AA) Bus interface TEMP [H'40] ADDRn H [H'AA] Lower byte read ADDRn L [H'40] CPU (H'40) Bus interface Module internal data bus TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] n = A to D Figure 20.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 5.00, 09/03, page 622 of 760 20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 20.4.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF bit to 0, first read ADF when ADF = 1, then write 0 to the ADF bit. When the mode or analog input channel must be switched during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 20.3 shows a timing diagram for this example. (The ADCSR register specifies bits in the operation example.) 1. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 to the ADF flag. 6. The routine reads and processes the conversion result (ADDRB = 0). 7. Execution of the A/D interrupt handling routine ends. Then, when the ADST bit is set to 1, A/D conversion starts and steps 2 to 7 are executed. Rev. 5.00, 09/03, page 623 of 760 Set ADIE Set ADST A/D conversion starts ADF Waiting Waiting A/D conversion 1 Waiting Waiting Waiting A/D conversion result 2 Waiting Clear* Clear Set Rev. 5.00, 09/03, page 624 of 760 Read result A/D conversion result 1 Read result A/D conversion result 2 Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA Note: * Vertical arrows ( ) indicate instruction execution by software. ADDRB ADDRC Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ADDRD 20.4.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing A/D conversions on one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. When A/D conversions end on the selected channels, the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 20.4 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1, SCN = 0), channel group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. Rev. 5.00, 09/03, page 625 of 760 A/D conversion Set* ADST ADF Clear Clear* Rev. 5.00, 09/03, page 626 of 760 Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 2 A/D conversion result 3 Waiting Waiting Waiting Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA Note: * Vertical arrows ( ) indicate instruction execution by software. ADDRB Figure 20.4 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) ADDRC ADDRD 20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1)). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) in group 0 are selected in scan mode are described next. Figure 20.5 shows a timing diagram for this example. 1. Scan mode is selected (MULTI = 1, SCN = 1), channel group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 5.00, 09/03, page 627 of 760 Continuous A/D conversion Set*1 Clear*1 ADST Clear*1 ADF Waiting Waiting A/D conversion 1 Waiting Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 4 A/D conversion 5 Waiting A/D conversion 4 Waiting Waiting Rev. 5.00, 09/03, page 628 of 760 A/D conversion result 2 A/D conversion result 3 Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC Figure 20.5 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ADDRD Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. Data during conversion is ignored. 20.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.6 shows the A/D conversion timing. Table 20.4 indicates the A/D conversion time. As indicated in figure 20.6, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 20.4. In multi mode and scan mode, the conversion time values given in table 20.4 apply to the first conversion. In the second and subsequent conversions, the conversion time is fixed at 512 states when CKS = 0 in ADCSR, or 256 states when CKS = 1. In both cases, the CKS bit should be set according to the P frequency so that the conversion time is within the range shown in table 23.10 in section 23, Electrical Characteristics. *1 P Address Write signal Input sampling timing *2 ADF tD tSPL tCONV Legend tD tSPL tCONV Notes: A/D conversion start delay Input sampling time A/D conversion time 1. ADCSR write cycle 2. ADCSR address Figure 20.6 A/D Conversion Timing Rev. 5.00, 09/03, page 629 of 760 Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 Symbol A/D conversion start delay Input sampling time A/D conversion time tD tSPL tCONV Min 17 -- 514 Typ -- 129 -- Max 28 -- 525 Min 10 -- 259 CKS = 1 Typ -- 65 -- Max 17 -- 266 Note: Values in the table are numbers of states (tcyc). 20.4.5 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE1 and TRGE0 bits are set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 20.7 shows the timing. P ADTRG External trigger signal ADST A/D conversion Figure 20.7 External Trigger Input Timing Rev. 5.00, 09/03, page 630 of 760 20.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 20.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * Offset error * Full-scale error * Quantization error * Nonlinearity error These four error quantities are explained below with reference to figure 20.8. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 20.8, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 20.8, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 20.8, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 20.8, item (4)). Note that it does not include offset, full-scale, or quantization error. Rev. 5.00, 09/03, page 631 of 760 Digital output Ideal A/D conversion characteristic Digital output Ideal A/D conversion characteristic (2) Full-scale error 111 110 101 100 011 010 001 000 (4) Nonlinearity error (3) Quantization error 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage Actual A/D convertion characteristic FS Analog input voltage (1) Offset error Figure 20.8 Definitions of A/D Conversion Accuracy 20.7 Usage Notes When using the A/D converter, note the following points. 20.7.1 Setting Analog Input Voltage * Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AV SS ANn AVCC (n = 0 to 7). * Relationships of AVCC and AVSS: AVCC and AVSS should be related as follows: AVCC = VCC 0.3 V and AVSS = VSS. 20.7.2 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0 to AN7), connect an input protection circuit like the one shown in figure 20.9. The circuit shown also includes an CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be selected according to actual application conditions. Table 20.5 lists the analog input pin specifications and figure 20.10 shows an equivalent circuit diagram of the analog input ports. Rev. 5.00, 09/03, page 632 of 760 20.7.3 Access Size and Read Data Table 20.6 shows the relationship between access size and read data. Note the read data obtained with different access sizes, bus widths, and endian modes. The case is shown here in which H'3FF is obtained when AV CC is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. AVCC 100 * 0.1 F SH7709S AN0 to AN7 AVSS Note: * 10 F 0.01 F Figure 20.9 Example of Analog Input Protection Circuit 1.0 k AN0 to AN7 20 pF 1 M Figure 20.10 Analog Input Pin Equivalent Circuit Rev. 5.00, 09/03, page 633 of 760 Table 20.5 Analog Input Pin Ratings Item Analog input capacitance Allowable signal-source impedance Min -- -- Max 20 5 Unit pF k Table 20.6 Relationship between Access Size and Read Data Bus Width 32 Bits (D31-D0) Access Size Byte access 16 Bits (D15-D0) Endian Command MOV.L#ADDRAH,R9 MOV.B@R9,R8 MOV.L#ADDRAL,R9 MOV.B@R9,R8 MOV.L#ADDRAH,R9 MOV.W@R9,R8 MOV.L#ADDRAL,R9 MOV.W@R9,R8 Longword MOV.L#ADDRAH,R9 access MOV.L@R9,R8 Big Little Big Little FFFF C0C0 FFxx Big FF C0 FF xx C0 xx FF xx C0 xx Little FF C0 xx FF xx C0 xx C0 xx FF 8 Bits (D7-D0) FFFFFFFF FFFFFFFF FFFF C0C0C0C0 C0C0C0C0 C0C0 FFxxFFxx FFxxFFxx FFxx Word access C0xxC0xx C0xxC0xx C0xx C0xx FFxxC0xx FFxxC0xx Ffxx C0xx C0xx FFxx In this table: #ADDRAH .EQU H'04000080 #ADDRAL .EQU H'04000082 Values are shown in hexadecimal for the case where read data is output to an external device via R8. Rev. 5.00, 09/03, page 634 of 760 Section 21 D/A Converter 21.1 Overview The SH7709S includes a D/A converter with two channels. 21.1.1 Features D/A converter features are listed below. * Eight-bit resolution * Two output channels * Conversion time: maximum 10 s (with 20-pF capacitive load) * Output voltage: 0 V to AVcc 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the D/A converter. Module data bus AVCC DADR0 DADR1 DACR DA1 DA0 AVSS 8-bit D/A Control circuit Legend DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 21.1 Block Diagram D/A Converter Rev. 5.00, 09/03, page 635 of 760 Bus interface On-chip data bus 21.1.3 I/O Pins Table 21.1 summarizes the D/A converter's input and output pins. Table 21.1 D/A Converter Pins Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Abbreviation AVcc AVss DA0 DA1 I/O Input Input Output Output Function Analog power supply Analog ground and reference voltage Analog output, channel 0 Analog output, channel 1 21.1.4 Register Configuration Table 21.2 summarizes the D/A converter's registers. Table 21.2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Abbreviation DADR0 DADR1 DACR R/W R/W R/W R/W Initial Value H'00 H'00 H'1F Address* 1 H'040000A0 2 (H'A40000A0)* H'040000A2 2 (H'A40000A2)* H'040000A4 2 (H'A40000A4)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Lower 16 bits of the address 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00, 09/03, page 636 of 760 21.2 21.2.1 Register Descriptions D/A Data Registers 0 and 1 (DADR0/1) Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset. 21.2.2 D/A Control Register (DACR) Bit: Initial value: R/W: 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7: DAOE1 0 1 Description DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled (Initial value) Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6: DAOE0 0 1 Description DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled (Initial value) Rev. 5.00, 09/03, page 637 of 760 Bit 5--D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When the chip enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion. To reduce the analog power-supply current in standby mode, clear the DAOE0 and DAOE1 bits and disable the D/A output. Bit 7: DAOE1 0 0 0 1 1 1 Bit 6: DAOE0 0 1 1 0 0 1 Bit 5: DAE -- 0 1 0 1 -- Description D/A conversion is disabled in channels 0 and 1 (Initial value) D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1 When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. Bits 4 to 0--Reserved: Read-only bits, always read as 1. Rev. 5.00, 09/03, page 638 of 760 21.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 21.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. The output value is (DADR0 contents/256) x AVcc. Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address bus DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 DA0 High-impedance state tDCONV Legend tDCONV : D/A conversion time Conversion result 1 tDCONV Figure 21.2 Example of D/A Converter Operation Rev. 5.00, 09/03, page 639 of 760 Rev. 5.00, 09/03, page 640 of 760 Section 22 User Debugging Interface (UDI) 22.1 Overview This LSI incorporates a User debugging interface (UDI) and advanced user debugger (AUD) for program debugging. 22.2 User Debugging Interface (UDI) The UDI (User debugging interface) performs on-chip debugging which is supported by this LSI. The UDI described here is a serial interface which is compatible with JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture) specifications. The UDI in the SH7709S supports a boundary scan mode, and is also used for emulator connection. When using an emulator, UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. 22.2.1 Pin Descriptions TCK: UDI serial data input/output clock pin. Data is serially supplied to the UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. TMS: Mode select input pin. The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol complies with the JTAG standard (IEEE Std. 1149.1). TRST: UDI reset input pin. Input is accepted asynchronously with respect to TCK, and when low, the UDI is reset. See section 22.4.2, Reset Configuration, for more information. TDI: UDI serial data input pin. Data transfer to the UDI is executed by changing this signal in synchronization with TCK. TDO: UDI serial data output pin. Data output from the UDI is executed by reading this signal in synchronization with TCK. ASEMD0: ASE mode select pin. If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. When using on the user system alone, without an emulator and the UDI, hold this pin at high level. In ASE Rev. 5.00, 09/03, page 641 of 760 mode, boundary scan and emulator functions can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. ASEBRKAK: Dedicated emulator pin KAK 22.2.2 Block Diagram Figure 22.1 shows a block diagram of the UDI. TDI SDBSR SDBPR Shift register SDIR TDO MUX TCK TMS TRST TAP controller Decoder Local bus Figure 22.1 Block Diagram of UDI 22.3 Register Descriptions The UDI has the following registers. * SDBPR: Bypass register * SDIR: Instruction register * SDBSR: Boundary scan register Rev. 5.00, 09/03, page 642 of 760 Table 22.1 shows the UDI register configuration. Table 22.1 UDI Registers CPU Side Name Bypass register Instruction register Boundary register Abbreviation SDBPR SDIR SDBSR R/W -- R -- Size -- 16 -- Address -- H'04000200 -- UDI Side R/W R/W R/W R/W Size 1 16 -- Initial Value* Undefined H'FFFF Undefined Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state. 22.3.1 Bypass Register (SDBPR) The bypass register is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass mode, SDBPR is connected between UDI pins TDI and TDO. 22.3.2 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its initial state. It is initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register Bit: Initial value: Bit: Initial value: 15 TI3 1 7 -- 1 14 TI2 1 6 -- 1 13 TI1 1 5 -- 1 12 TI0 1 4 -- 1 11 -- 1 3 -- 1 10 -- 1 2 -- 1 9 -- 1 1 -- 1 8 -- 1 0 -- 1 Bits 15 to 12--Test Instruction Bits (TI3 to TI0): Cannot be written by the CPU. Rev. 5.00, 09/03, page 643 of 760 Table 22.2 UDI Commands Bit 15 to 12 TI3 0 0 0 0 0 1 1 1 1 1 0 TI2 0 1 1 1 1 0 0 1 1 1 0 TI1 0 0 0 1 1 0 1 0 1 1 0 TI0 0 0 1 0 1 -- -- -- 0 1 1 Description EXTEST SAMPLE/PRELOAD Reserved UDI reset negate UDI reset assert Reserved UDI interrupt Reserved Reserved Bypass mode Recovery from sleep (Initial value) Bits 11 to 0--Reserved: These bits are always read as 1. 22.3.3 Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register, located on the PAD, for controlling the input/output pins of the SH7709S. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 22.3 shows the correspondence between the pins of this LSI and boundary scan register bits. Rev. 5.00, 09/03, page 644 of 760 Table 22.3 Pins of this LSI and Boundary Scan Register Bits Bit from TDI 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Pin Name I/O Bit 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 Pin Name D1 D0 MD1 MD2 NMI IRQ0/IRL0/PTH0 IRQ1/IRL1/PTH1 IRQ2/IRL2/PTH2 IRQ3/IRL3/PTH3 IRQ4/PTH4 D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 D12 D11 I/O IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00, 09/03, page 645 of 760 Bit 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 Pin Name D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Bit 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 Pin Name D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BS/PTK4 WE2/DQMUL/ICIORD/ PTK6 WE3/DQMUU/ICIORD/ PTK7 AUDSYNC/PTE7 CS2/PTK0 CS3/PTK1 CS4/PTK2 CS5/CE1A/PTK3 CE2A/PTE4 CE2B/PTE5 A0 A1 A2 A3 A4 A5 A6 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT Rev. 5.00, 09/03, page 646 of 760 Bit 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 Pin Name A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 BS/PTK4 RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTK6 WE3/DQMUU/ICIOWR/ PTK7 RD/WR AUDSYNC/PTE7 CS0/MCS0 CS2/PTK0 CS3/PTK1 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 Pin Name CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 CE2B/PTE5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 I/O OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 5.00, 09/03, page 647 of 760 Bit 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 Pin Name A25 BS/PTK4 RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTK6 WE3/DQMUU/ICIOWR/ PTK7 RD/WR AUDSYNC/PTE7 CS0/MCS0 CS2/PTK0 CS3/PTK1 CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 CE2B/PTE5 CKE/PTK5 RAS3L/PTJ0 PTJ1 CASL/PTJ2 CASU/PTJ3 PTJ4 PTJ5 DACK0/PTD5 DACK1/PTD7 PTE6 PTE3 RAS3U/PTE2 PTE1 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN Bit 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 Pin Name BREQ WAIT AUDCK/PTH6 IOIS16/PTG7 ASEBRKAK/PTG5 CKIO2/PTG4 AUDATA3/PTG3 AUDATA2/PTG2 AUDATA1/PTG1 AUDATA0/PTG0 ADTRG/PTH5 IRLS3/PTF3/PINT11 IRLS2/PTF2/PINT10 IRLS1/PTF1/PINT9 IRLS0/PTF0/PINT8 MD0 CKE/PTK5 RAS3L/PTJ0 PTJ1 CASL/PTJ2 CASU/PTJ3 PTJ4 PTJ5 DACK0/PTD5 DACK1/PTD7 PTE6 PTE3 RAS3U/PTE2 PTE1 BACK I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00, 09/03, page 648 of 760 Bit 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 Pin Name ASEBRKAK/PTG5 AUDATA3/PTG3 AUDATA2/PTG2 AUDATA1/PTG1 AUDATA0/PTG0 CKE/PTK5 RAS3L/PTJ0 PTJ1 CASL/PTJ2 CASU/PTJ3 PTJ4 PTJ5 DACK0/PTD5 DACK1/PTD7 PTE6 PTE3 RAS3U/PTE2 PTE1 BACK ASEBRKAK/PTG5 AUDATA3/PTG3 AUDATA2/PTG2 AUDATA1/PTG1 AUDATA0/PTG0 STATUS0/PTJ6 STATUS1/PTJ7 TCLK/PTH7 SCK0/SCPT1 SCK1/SCPT3 SCK2/SCPT5 RTS2/SCPT6 RxD0/SCPT0 I/O OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN Bit 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 Pin Name RxD2/SCPT4 WAKEUP/PTD3 RESETOUT/PTD2 DRAK0/PTD1 DRAK1/PTD0 DREQ0/PTD4 DREQ1/PTD6 RxD1/SCPT2 CTS2/IRQ5/SCPT7 MCS7/PTC7/PINT7 MCS6/PTC6/PINT6 MCS5/PTC5/PINT5 MCS4/PTC4/PINT4 MCS3/PTC3/PINT3 MCS2/PTC2/PINT2 MCS1/PTC1/PINT1 MCS0/PTC0/PINT0 MD3 MD4 MD5 STATUS0/PTJ6 STATUS1/PTJ7 TCLK/PTH7 IRQOUT TxD0/SCPT0 SCK0/SCPT1 TxD1/SCPT2 SCK1/SCPT3 TxD2/SCPT4 SCK2/SCPT5 RTS2/SCPT6 MCS7/PTC7/PINT7 I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00, 09/03, page 649 of 760 Bit 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Pin Name MCS6/PTC6/PINT6 MCS5/PTC5/PINT5 MCS4/PTC4/PINT4 WAKEUP/PTD3 RESETOUT/PTD2 MCS3/PTC3/PINT3 MCS2/PTC2/PINT2 MCS1/PTC1/PINT1 MCS0/PTC0/PINT0 DRAK0/PTD1 DRAK1/PTD0 STATUS0/PTJ6 STATUS1/PTJ7 TCLK/PTH7 IRQOUT TxD0/SCPT0 SCK0/SCPT1 TxD1/SCPT2 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to TDO Pin Name SCK1/SCPT3 TxD2/SCPT4 SCK2/SCPT5 RTS2/SCPT6 MCS7/PTC7/PINT7 MCS6/PTC6/PINT6 MCS5/PTC5/PINT5 MCS4/PTC4/PINT4 WAKEUP/PTD3 RESETOUT/PTD2 MCS3/PTC3/PINT3 MCS2/PTC2/PINT2 MCS1/PTC1/PINT1 MCS0/PTC0/PINT0 DRAK0/PTD1 DRAK1/PTD0 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Note: Control is an active-low signal. When Control is driven low, the corresponding pin is driven by the value of OUT. Rev. 5.00, 09/03, page 650 of 760 22.4 22.4.1 UDI Operation TAP Controller Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 1 Select-DR-scan 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 0 1 0 Run-test/idle Figure 22.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. The TDO value changes at the TCK falling edge. The TDO is at high impedance, except with shiftDR (shift-SR) and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. Rev. 5.00, 09/03, page 651 of 760 22.4.2 Reset Configuration Table 22.4 Reset Configuration ASEM ASEMD0 * High-level 1 RESETP ESET Low-level High-level TRST Low-level High-level Low-level High-level Low-level High-level Chip State Normal reset and UDI reset Normal reset UDI reset only Normal operation 2 Reset hold* ASE user mode* : Normal reset 3 ASE break mode* : RESETP assertion masked UDI reset only Normal operation 3 Low-level Low-level High-level Low-level High-level Notes: 1. Selects main chip mode or ASE mode ASEMD0 = H, normal mode ASEMD0 = L, ASE mode Set ASEMD0 = H when using on the user system alone, without an emulator and the UDI. 2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a constant cycle. In this state, the CPU does not start up, even if RESETP is driven high. When TRST is driven high, UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by the following: * Boot request from UDI * Another RESETP assert (power-on reset) 3. There are two ASE modes, one for executing software in the emulator's firmware (ASE break mode) and one for executing user software (ASE user mode). Rev. 5.00, 09/03, page 652 of 760 22.4.3 UDI Reset An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the same kind as a power-on reset. An UDI reset is released by inputting an UDI reset negate command. SDIR UDI reset assert UDI reset negate Chip internal reset CPU state Branch to H'A0000000 Figure 22.3 UDI Reset 22.4.4 UDI Interrupt The UDI interrupt function generates an interrupt by setting a command from the UDI in the SDIR. An UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a fixed priority level of 15. UDI interrupts are not accepted in sleep mode or standby mode. 22.4.5 Bypass The JTAG-based bypass mode for the UDI pins can be selected by setting a command from the UDI in SDIR. 22.4.6 Using UDI to Recover from Sleep Mode It is possible to recover from sleep mode by setting a command (0001) from the UDI in SDIR. Rev. 5.00, 09/03, page 653 of 760 22.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in the boundary scan mode stipulated by JTAG. 22.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The instruction code is 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Rev. 5.00, 09/03, page 654 of 760 Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. 22.5.2 Points for Attention 1. Boundary scan mode covers clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO). 2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM, CA). 3. Boundary scan mode does not cover UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. When a boundary scan test is carried out, ensure that the CKIO clock operates constantly. The CKIO frequency range is as follows: Minimum: 1 MHz Maximum: Maximum frequency for respective clock mode specified in the CPG section Set pins MD[2:0] to the clock mode to be used. After powering on, wait for the CKIO clock to stabilize before performing a boundary scan test. 5. Fix the RESETP pin low. 6. Fix the CA pin high, and the ASEMD0 pin low. 22.6 Usage Notes 1. An UDI command other than an UDI interrupt, once set, will not be modified as long as another command is not re-issued from the UDI. An UDI interrupt command, however, will be changed to a bypass command once set. 2. Because chip operations are suspended in standby mode, UDI commands are not accepted. However, the TAP controller remains in operation at this time. 3. The UDI is used for emulator connection. Therefore, UDI functions cannot be used when using an emulator. 22.7 Advanced User Debugger (AUD) The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD. Rev. 5.00, 09/03, page 655 of 760 Rev. 5.00, 09/03, page 656 of 760 Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 shows the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Symbol VccQ Rating -0.3 to 4.2 -0.3 to 2.5 Unit V V Power supply voltage (internal) Vcc Vcc - PLL1 Vcc - PLL2 Vcc - RTC Input voltage (except port L) Input voltage (port L) Analog power-supply voltage Analog input voltage Operating temperature Storage temperature Vin Vin AVcc VAN Topr Tstr -0.3 to VccQ + 0.3 -0.3 to AVcc + 0.3 -0.3 to 4.6 -0.3 to AVcc + 0.3 -20 to 75 -55 to 125 V V V V C C Caution: Operating the chip in excess of the absolute maximum rating may result in permanent damage. * Order of turning on 1.7 V/1.8 V/1.9 V/2.0 V power (Vcc, Vcc-PLL1, Vcc-PLL2, Vcc-RTC) and 3.3 V power (VccQ, AVcc): 1. First turn on the 3.3 V power, then turn on the 1.7 V/1.8 V/1.9 V/2.0 V power within 1 ms. This interval should be as short as possible. 2. Until voltage is applied to all power supplies, a low level is input at the RESETP pin, and CKIO has operated for a maximum of 4 clock cycles, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. Note that the RESETP pin cannot receive a low level signal while a low level signal is being input to the CA pin. Waveforms at power-on are shown in the following figure. Rev. 5.00, 09/03, page 657 of 760 (Max. 1 ms) 3.3 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V 1.7 V/1.8 V/1.9 V/2.0 V power RESETP Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence * Power-off order 1. In the reverse order of powering-on, first turn off the 1.7 V/1.8 V/1.9 V/2.0 V power, then turn off the 3.3 V power within 1 ms. This interval should be as short as possible. 2. Pin states are undefined while only the 1.7 V/1.8 V/1.9 V/2.0 V power is off. The system design must ensure that these undefined states do not cause erroneous system operation. Rev. 5.00, 09/03, page 658 of 760 23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics Ta = -20 to 75C Item Power supply voltage Symbol VccQ Vcc, Vcc-PLL1, Vcc-PLL2, Vcc-RTC Current dissipation Normal Icc operation Min 3.0 1.85 1.75 1.65 1.55 -- -- -- IccQ Sleep 1 mode* Icc IccQ -- -- -- Typ 3.3 2.00 1.90 1.80 1.70 410 330 250 190 20 15 10 Max 3.6 2.15 2.05 2.05 1.95 680 540 410 310 40 30 20 mA Unit V 200 MHz model* 167 MHz model 133 MHz model 100 MHz model Vcc = 2.0 V, I = 200 MHz Vcc = 1.9 V, I = 167 MHz Vcc = 1.8 V, I = 133 MHz Vcc = 1.7 V, I = 100 MHz VccQ = 3.3 V, B = 33 MHz *1 When there is no other external bus cycle other than the refresh cycle. Vcc = 1.9 V, VccQ = 3.3 V B = 33MHz Standby mode Icc IccQ Icc IccQ -- -- -- -- 40 10 290 10 120 30 900 30 A Ta = 25C (RTC on) VccQ = 3.3 V, Vcc = 1.55 V to 2.15 V Ta = 25C (RTC off), Crystal is not used. VccQ = 3.3 V, Vcc = 1.55 V to 2.15 V Measurement Conditions Rev. 5.00, 09/03, page 659 of 760 Item Symbol Min VccQ x 0.9 Typ -- Max Unit Measurement Conditions Input high RESETP, VIH voltage RESETM, NMI, IRQ5 to IRQ0, MD5 to MD0, IRL3 to IRL0, IRLS3 to IRLS0, PINT15 to PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, RxD1, CA EXTAL2 VccQ + V 0.3 -- -- -- When not connecting to a crystal oscillator, connect to Vcc. Port L Other input pins 2.0 2.0 -- -- AVcc + 0.3 VccQ + 0.3 Rev. 5.00, 09/03, page 660 of 760 Item Symbol Min -0.3 Typ -- Max VccQ x 0.1 Unit V Measurement Conditions Input low RESETP, VIL voltage RESETM, NMI, IRQ5-IRQ0, MD5-MD0, IRL3 to IRL0, IRLS3 to IRLS0, PINT15- PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, RxD1, CA EXTAL2 -- -- -- When not connecting to a crystal oscillator, connect to Vcc. Port L Other input pins Input leak All input pins I Iin I current ThreeI/O, all state leak output pins current (off condition) Output high voltage All output pins I Isti I -0.3 -0.3 -- -- -- -- -- -- AVcc x 0.2 VccQ x 0.2 1.0 1.0 A A Vin = 0.5 to VccQ-0.5 V Vin = 0.5 to VccQ-0.5 V VOH 2.4 -- -- V VccQ = 3.0 V, IOH = -200 A 2.0 Output low All output voltage pins Pull-up Port pin resistance Pin capacity All pins VOL Rpull C -- 30 -- -- -- 60 -- -- 0.55 120 10 k pF VccQ = 3.0 V, IOH = -2 mA VccQ = 3.6 V, IOL = 1.6 mA Rev. 5.00, 09/03, page 661 of 760 Item Analog powersupply voltage Analog powersupply current During A/D conversion During A/D and D/A conversion Idle Symbol Min AVcc 3.0 Typ 3.3 Max 3.6 Unit V Measurement Conditions AIcc -- 0.8 2 mA -- 2.4 6 mA -- 1 20 A Ta = 25C Notes: Even when PLL is not used, always connect Vcc-PLL1 and Vcc-PLL2 to Vcc and connect Vss-PLL1 and Vss-PLL2 to Vss. Even when RTC is not used, always supply power between Vcc-RTC and Vss-RTC. AVcc must be under condition of VccQ - 0.3 V AVcc VccQ + 0.3 V. If the A/D and D/A converters are not used, do not leave the AVcc and AVss pins open. Connect AVcc to VccQ, and connect AVss to VssQ. Current dissipation values shown are the values at which all output pins are without load under conditions of VIH min = VccQ - 0.5 V, VIL max = 0.5 V. The same voltage should be supplied to Vcc, Vcc-RTC, Vcc-PLL1, and Vcc-PLL2. * If the IRL and IRLS interrupts are used, the minimum is 1.9 V. Table 23.3 Permitted Output Current Values VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 120 2.0 40 Unit mA mA mA mA Caution: To ensure LSI reliability, do not exceed the value for output current given in table 23.3. Rev. 5.00, 09/03, page 662 of 760 23.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 23.4 Operating Frequency Range VccQ = 3.3 0.3 V, VccQ = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Operating frequency CPU, cache, TLB Symbol f Min 30 25 Typ -- Max 200 167 133 100 External bus 30 25 -- 66.67 Unit MHz Remarks 200 MHz model 167 MHz model 133 MHz model 100 MHz model 200 MHz model 167 MHz model 133 MHz model 100 MHz model -- 33.34 200 MHz model 167 MHz model 133 MHz model 100 MHz model Peripheral module 7.5 6.25 Rev. 5.00, 09/03, page 663 of 760 23.3.1 Clock Timing Table 23.5 Clock Timing VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item EXTAL clock input frequency (clock mode 0) EXTAL clock input cycle time (clock mode 0) EXTAL clock input frequency (clock mode 1) EXTAL clock input cycle time (clock mode 2) EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time RESETM setup time RESETP assert time RESETM assert time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time 1 (standby canceled) PLL synchronization settling time 2 (multiplication rete modified) IRQ/IRL interrupt determination time (RTC used and standby mode) Symbol fEX tEXcyc fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK20R tCK20F tOSC1 tRESPS tRESMS tRESPW tRESMW tOSC2 tOSC3 tOSC4 tPLL1 tPLL2 tIRLSTB Min 25 15 6.25 60 1.5 1.5 -- -- 20 15.2 1.5 1.5 -- -- 25 15.2 3 3 -- -- -3 -- -- 10 20 6 20 20 10 10 11 100 100 100 Max 66.67 40 16.67 160 -- -- 6 6 66 40 -- -- 6 6 66 40 -- -- 5 5 3 7 7 -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 23.5 23.6 23.7 23.8, 23.9 23.10 23.9 23.4 23.4, 23.5 23.3 23.2 Figure 23.1 Rev. 5.00, 09/03, page 664 of 760 tEXcyc EXTAL* (input) 1/2 VCCQ tEXH tEXL VIH 1/2 VCCQ tEXR VIH VIH VIL tEXF VIL Note: * The clock input from the EXTAL pin. Figure 23.1 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCCQ VIH VIL tCKIF tCKIL VIH VIL VIH 1/2 VCCQ tCKIR Figure 23.2 CKIO Clock Input Timing tcyc tCKOH CKIO (output) tCKOL 1/2VCCQ VOH VOH VOL tCKOF VOH VOL 1/2VCCQ tCKOR tCK2D CKIO2 (output) tCK2D VOH VOH VOL tCK2OF VOH VOL tCK2OR Figure 23.3 CKIO Clock Output Timing Rev. 5.00, 09/03, page 665 of 760 Stable oscillation CKIO, internal clock VCC VCC min tOSC1 RESETP Note: Oscillation settling time when built-in oscillator is used tRESPW tRESPS Figure 23.4 Power-on Oscillation Settling Time Standby CKIO, internal clock tOSC2 RESETP RESETM Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode tRESPW/MW tRESPS/MS Stable oscillation Figure 23.5 Oscillation Settling Time at Standby Return (Return by Reset) Rev. 5.00, 09/03, page 666 of 760 Standby CKIO, internal clock tOSC3 Stable oscillation NMI WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.6 Oscillation Settling Time at Standby Return (Return by NMI) Standby CKIO, internal clock tOSC4 IRL3 to IRL0 IRQ4 to IRQ0 PINT0/1 Stable oscillation WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode (only when RTC is used) Figure 23.7 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0, PINT0/1, IRL3 to IRL0) Rev. 5.00, 09/03, page 667 of 760 Reset or NMI interrupt request Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output Stable input clock tPLL1 PLL synchronization Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO pin Figure 23.8 PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) IRQ4 - IRQ0/IRL3 - IRL0 interrupt request Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output Stable input clock tIRLSTB tPLL1 PLL synchronization Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO pin Figure 23.9 PLL Synchronization Settling Time during Standby Recovery (IRQ/IRL or PINT0/PINT1 Interrupt) Rev. 5.00, 09/03, page 668 of 760 Multiplication rate modified EXTAL input*1 (CKIO input) tPLL2 CKIO output*2 (PLL output) Internal clock Notes: 1. CKIO input in clock mode 7 2. PLL output in other than clock mode 7 Figure 23.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified Rev. 5.00, 09/03, page 669 of 760 23.3.2 Control Signal Timing Table 23.6 Control Signal Timing Vcc = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item RESETP pulse width 1 RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time 1 NMI setup time * NMI hold time IRQ5-IRQ0 setup time IRQ5-IRQ0 hold time IRQOUT delay time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 *1 Symbol tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH tNMIS tNMIH tIRQS tIRQH tIRQOD tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 Min 2 20 * Max -- -- -- 3 Unit tcyc ns ns tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 23.11, 23.12 20 4 20 * 6 34 6 4 10 4 10 4 -- -- -- 0 0 0 0 -- -- -- -- -- -- -- -- -- 10 10 10 15 15 15 15 23.14 23.12 23.13 23.14, 23.15 Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. 2. In the standby mode, tRESPW = tOSC1 (100 s) when XTAL oscillation is continued and tRESPW = tOSC2 (10 ms) when XTAL oscillation is off. In the sleep mode, tRESPW = tPLL1 (100 s). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 s). 3. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH). Rev. 5.00, 09/03, page 670 of 760 CKIO tRESPS/MS tRESPW/MW RESETP RESETM tRESPS/MS Figure 23.11 Reset Input Timing CKIO tRESPH/MH RESETP RESETM tNMIH NMI tIRQH IRQ5 to IRQ0 VIL tRESPS/MS VIH VIL tNMIS VIH VIL tIRQS VIH Figure 23.12 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT Figure 23.13 IRQOUT Timing QOUT Rev. 5.00, 09/03, page 671 of 760 CKIO tBREQH tBREQS BREQ tBACKD BACK RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn A25 to A0, D31 to D0 tBOFF2 tBON2 tBACKD tBREQH tBREQS tBOFF1 tBON1 Figure 23.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO tSTD STATUS 0 STATUS 1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn A25 to A0, D31 to D0 tBON2 tSTD tBOFF1 tBON1 Figure 23.15 Pin Drive Timing at Standby Rev. 5.00, 09/03, page 672 of 760 23.3.3 AC Bus Timing Table 23.7 Bus Timing Clock Modes 0/1/2/7, VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Address delay time Address setup time 1 Address hold time* BS delay time CS delay time 1 CS delay time 2 CS delay time (SDRAM access) Read/write delay time Read/write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 2 Read data hold time 1* Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data hold time 1 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time WAIT hold time RAS delay time 2 CAS delay time 2 DQM delay time CKE delay time Symbol tAD tAS tAH tBSD tCSD1 tCSD2 tCSD3 tRWD tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDH1 tWDH2 tWDH3 tWDH4 tWTS tWTH tRASD2 tCASD2 tDQMD tCKED Min 1.5 0 4 -- 0 -- 1.5 1.5 0 -- 6 5 0 1 -- -- 1.5 1.5 1.5 2 2 5 0 1.5 1.5 1.5 1.5 Max 12 -- -- 10 10 10 10 10 -- 10 -- -- -- -- 10 14 12 -- -- -- -- -- -- 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 23.16-23.36, 23.39-23.46 23.16-23.18 23.16-23.21 23.16-23.36, 23.40-23.46 23.16-23.21, 23.40-23.46 23.16-23.21 23.22-23.39 23.16-23.46, 23.39-23.46 23.16-23.21 23.16-23.21 23.40-23.43 23.16-23.21, 23.40-23.46 23.22-23.25, 23.30-23.33 23.16-23.21, 23.40-23.46 23.22-23.25, 23.30-23.33 23.16-23.18, 23.40, 23.41 23.16-23.18, 23.40, 23.41, 23.44-23.46 23.26-23.29, 23.34-23.36 23.16-23.18, 23.40, 23.41, 23.44-23.46 23.26-23.29, 23.34-23.36 23.16-23.18 23.40, 23.41, 23.44-23.46 23.17-23.21, 23.41, 23.43, 23.45, 23.46 23.17-23.21, 23.41, 23.43, 23.45, 23.46 23.22-23.39 23.22-23.39 23.22-23.36 23.38 Rev. 5.00, 09/03, page 673 of 760 Item ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time Symbol tICRSD tICWSD tIO16S tIO16H Min -- -- 6 4 -- -- Max 10 10 -- -- 10 10 Unit ns ns ns ns ns ns Figure 23.44-23.46 23.44-23.46 23.45, 23.46 23.45, 23.46 23.16-23.36, 23.39-23.46 23.16-23.22 DACK delay time 1 tDAKD1 (Reference for CKIO rise) DACK delay time 2 tDAKD2 (Reference for CKIO fall) Notes: 1. Specified based on the slowest negate timing for CSn, RD, or WEn 2. Specified based on whichever negate timing is faster, CSn or RD. Rev. 5.00, 09/03, page 674 of 760 23.3.4 Basic Timing T1 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tAH tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tWED tRWH tWDH3 tWDH1 tRSD tRWH tCSD2 tRWH tAS tAD T2 tRDH1 tRWD tRDH1 Figure 23.16 Basic Bus Cycle (No Wait) Rev. 5.00, 09/03, page 675 of 760 T1 Tw T2 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tDAKD1 tBSD tWED tAH tRWH tWDH3 tWDH1 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAS tAD tRDH1 Figure 23.17 Basic Bus Cycle (One Wait) Rev. 5.00, 09/03, page 676 of 760 T1 Tw Tw T2 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tAH tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tWTS tWTH tDAKD2 tBSD tWED tRWH tWDH3 tWDH1 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAS tAD tRDH1 Figure 23.18 Basic Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.00, 09/03, page 677 of 760 23.3.5 Burst ROM Timing T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WR tRSD RD tRDH1 tRDS D31 to D0 tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tWTS tWTH tWTS tWTH tDAKD2 tBSD tBSD tBSD tRDS1 tRDH1 tRSD tAH tRSD tRWD tAH tRSD tRWH tCSD2 tRWH tAD tAD Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. Figure 23.19 Burst ROM Bus Cycle (No Wait) Rev. 5.00, 09/03, page 678 of 760 T1 Tw Tw TB2 TB1 Tw TB2 T2 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD RD tRDH1 tRDS1 D31 to D0 tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD2 tBSD tBSD tBSD tRDS1 tRDH1 tRDH1 tRSD tAH tRSD tRSD tRSD tRWD tCSD2 tRWH tAD tAH tRWH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.20 Burst ROM Bus Cycle (Two Waits) Rev. 5.00, 09/03, page 679 of 760 T1 CKIO tAD A25 to A4 Tw Tw TB2 TB1 TBw T2 tAD tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WR tRSD RD tRDH1 tRDS1 D31 to D0 tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tWTS tWTH tWTS tWTH tDAKD2 tBSD tBSD tBSD tRDS tRDH1 tRSD1 tAH tRSD1 tAH tRSD tRWH tRWD tCSD2 tRWH Note: In the write cycle, the basic bus cycle is performed. Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.00, 09/03, page 680 of 760 23.3.6 Synchronous DRAM Timing Tr Tc1 Tc2 (Tpc) CKIO tAD Row address tAD tAD Read A command tAD Column address tCSD3 tAD tAD A25 to A16 A12 or A10 tAD A15 to A0 Row address tAD Row address tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 tDQMD tCASD2 tRASD2 tRWD D31 to D0 tBSD tBSD BS CKE tDAKD1 (High) tDAKD1 DACKn Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) Rev. 5.00, 09/03, page 681 of 760 Tr Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 Row address tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 tDQMD tCASD2 tRASD2 tRWD Row address tAD Column address tCSD3 Row address tAD tAD Read A command tAD tAD D31 to D0 tBSD BS tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) Rev. 5.00, 09/03, page 682 of 760 Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 Row address tAD Row address tAD Row address tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 tDQMD tCASD2 tRASD2 tRWD Column address (1-4) tCSD3 Read command tAD tAD Read A command tAD tAD D31 to D0 tBSD BS tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1) Rev. 5.00, 09/03, page 683 of 760 Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) CKIO tAD A25 to A16 tAD tAD Row address tAD tAD tAD tAD A12 or A10 Row address tAD Read command tAD Column address (1-4) tCSD3 tAD A15 to A0 Row address tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 tCASD2 tRASD2 tRWD CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 (read) tBSD BS tBSD tRDS2 tRDH2 tDQMD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0) Rev. 5.00, 09/03, page 684 of 760 Tr Tc1 (Trwl) (Tpc) CKIO tAD A25 to A16 tAD A12 or A10 tAD tAD Row address tAD Write A command tAD tAD Row address tAD A15 to A0 Row address tCSD3 Column address tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tBSD tWDH2 tDQMD tCASD2 tRASD2 tRWD tRWD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) Rev. 5.00, 09/03, page 685 of 760 Tr Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) CKIO tAD tAD A25 to A16 tAD A12 or A10 Row address tAD tAD tAD Write A command tAD tAD Column address tCSD1 Row address tAD tAD Row address tCSD1 A15 to A0 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tBSD tWDH2 tDQMD tCASD2 tRASD2 tRWD tRWD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) Rev. 5.00, 09/03, page 686 of 760 Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) CKIO tAD A25 to A16 tAD A12 or A10 tAD Row address tAD tAD tAD Row address tAD tAD Row address tCSD3 Write command Write A command tAD A15 to A0 Column address (1-4) tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tBSD tWDD2 tWDH2 tDQMD tCASD2 tRASD2 tRWD tRWD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) Rev. 5.00, 09/03, page 687 of 760 Tr Trw Tc1 Tc2 Tc3 Td4 (Trwl) (Tpc) CKIO tAD A25 to A16 tAD A12 or A10 Row address tAD Write command tAD tAD tAD Row address tAD tAD Row address tCSD3 Write A command tAD A15 to A0 Column address (1-4) tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 tWDD2 tWDH2 tDQMD tCASD2 tRASD2 tRWD tRWD D31 to D0 tBSD BS tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 23.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) Rev. 5.00, 09/03, page 688 of 760 Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tRDS2 tRDH2 tDQMD tCASD2 tRWD Column address tCSD3 Read command tAD Row address tAD tAD CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1) Rev. 5.00, 09/03, page 689 of 760 Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tRDS2 tRDH2 tDQMD tCASD2 tRWD Column address tCSD3 Read command tAD Row address tAD tAD CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2) Rev. 5.00, 09/03, page 690 of 760 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD A25 to A16 tAD tAD tAD Row address tAD tAD Row address tCSD3 CSn tRWD tRWD Row address tAD A12 or A10 Read command tAD Column address tCSD3 A15 to A0 tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD tDQMD tDQMD tCASD2 tRASD2 DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tRDS2 tRDH2 CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1) Rev. 5.00, 09/03, page 691 of 760 Tp Tpw Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD A25 to A16 tAD tAD tAD Row address tAD tAD Row address tCSD3 CSn tRWD tRWD Row address tAD A12 or A10 Read command tAD Column address tCSD3 A15 to A0 tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD tDQMD tDQMD tCASD2 tRASD2 tRASD2 tRASD2 DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tRDS2 tRDH2 CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) Rev. 5.00, 09/03, page 692 of 760 Tc1 Tc2 Tc3 Tc4 CKIO tAD tAD A25 to A16 tAD Row address tAD A12 or A10 tAD Write command tAD Column address tCSD3 tCSD3 A15 to A0 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD tDQMD tCASD2 tRASD2 tRWD DQMxx tWDD2 tWDD2 D31 to D0 tBSD BS tBSD CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) Rev. 5.00, 09/03, page 693 of 760 Tp Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD tAD A25 to A16 tAD tAD tAD Row address tAD tAD Row address tCSD3 CSn tRWD tRWD tRWD Row address tAD A12 or A10 Write command tAD Column address tCSD3 A15 to A0 tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD tDQMD tDQMD tCASD2 tRASD2 DQMxx tWDD2 tWDD2 D31 to D0 tBSD BS tBSD CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0) Rev. 5.00, 09/03, page 694 of 760 Tp Tpw Tr Trw Tc1 Tc2 Tc3 Td4 CKIO tAD tAD A25 to A16 tAD tAD tAD Row address tAD tAD Row address tCSD3 CSn tRWD tRWD Row address tAD A12 or A10 Write command tAD Column address tCSD3 tAD A15 to A0 tRWD tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD tDQMD tDQMD tCASD2 tRASD2 tRASD2 tRASD2 DQMxx tWDD2 tWDD2 D31 to D0 tBSD BS tBSD CKE (High) tDAKD1 tDAKD1 DACKn Figure 23.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1) Rev. 5.00, 09/03, page 695 of 760 Tp Tpc TRr TRrw TRrw (Tpc) (Tpc) CKIO CKE tCSD3 CSn tRASD2 RAS3x tRASD2 tCSD3 (High) tCSD3 tCSD3 tRASD2 tRASD2 tCASD2 CASxx tRWD RD/WR tRWD tCASD2 Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) Rev. 5.00, 09/03, page 696 of 760 Tp Tpc TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO t CKED CKE t CKED t CSD3 t CSD3 t CSD3 t CSD3 CSn t RASD2 t RASD2 t RASD2 t RASD2 RAS t CASD2 t CASD2 CAS t RWD RD/WR t RWD t RWD Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1) Rev. 5.00, 09/03, page 697 of 760 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO tAD tAD tAD A13 or A11 tAD A12 or A10 tAD A11 to A2 or A9 to A2 tCSD3 CSn tRWD RD/WR tRASD2 RAS tCASD2 CASxx tCASD2 tRASD2 tRASD2 tRASD2 tRWD tRWD tCSD3 tAD tAD tAD tAD tAD tAD D31 to D0 CKE (High) tDAKD1 DACKn tDAKD1 Figure 23.39 Synchronous DRAM Mode Register Write Cycle Rev. 5.00, 09/03, page 698 of 760 23.3.7 PCMCIA Timing Tpcm1 Tpcm2 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15 to D0 (read) tWED WE1 (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tWED tWDH4 tWDH1 tRSD tRWD tCSD1 tAD tRDH1 Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.00, 09/03, page 699 of 760 Tpcm0 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w tAD tCSD1 tRWD tRSD RD (read) tRSD tRDH1 tRDS1 D15 to D0 (read) tWED WE1 (write) tWED tWDH4 tWDH1 tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tBSD tDAKD1 tWTS tWTH tWTS tWTH WAIT Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.00, 09/03, page 700 of 760 Tpcm1 CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 tAD tAD tAD tAD tCSD1 tRWD tRSD tRSD tRSD tRDH1 tRDS1 tRDS1 tRDH1 D15 to D0 (read) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tBSD tBSD Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev. 5.00, 09/03, page 701 of 760 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15 to D0 (read) tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tWTS tWTH tDAKD1 tBSD tBSD tBSD tRSD tRSD tRSD tRWD tCSD1 tAD tAD tAD tRDH1 tRDS1 tRDH1 Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) Rev. 5.00, 09/03, page 702 of 760 Tpci1 Tpci2 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR tICRSD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tICWSD tICRSD tRWD tCSD1 tAD tRDH1 tWDH4 tWDH1 Figure 23.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.00, 09/03, page 703 of 760 Tpci0 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w tAD tCSD1 tRWD tICRSD ICIORD (read) tICRSD tRDH1 tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tIO16S tIO16H IOIS16 tWTS tWTH tDAKD1 tBSD tICWSD tWDH4 tWDH1 Figure 23.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.00, 09/03, page 704 of 760 Tpci0 CKIO tAD A25 to A4 tAD A0 tCSD1 CExx tRWD RD/WR Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w tAD tAD tAD tCSD1 tCSD1 tRWD tICRSD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tICRSD tICRSD tICRSD tRDH1 tRDS1 tRDH1 tICWSD tICWSD tICWSD tWDH4 tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tIO16S tIO16H IOIS16 tWTS tWTH tBSD tBSD tBSD tWDD1 tWDH4 tWDH1 tDAKD1 Figure 23.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1) Rev. 5.00, 09/03, page 705 of 760 23.3.8 Peripheral Module Signal Timing Table 23.8 Peripheral Module Signal Timing VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Module TMU, RTC Item Timer input setup time Timer clock input setup time Timer clock pulse width Edge specification Both edge specification Asynchronization Clock synchronization tSCKR tSCKF tSCKW tTXD tRXS tRXH tRTSD tCTSS tCTSH tPORTD tPORTS1 tPORTH1 tPORTS2 tPORTH2 tPORTS3 tPORTH3 tDRQS tDREQH tDRAKD Symbol tTCLKS tTCKS tTCKWH tTCKWL tROSC tSCYC Min 15 15 1.5 2.5 3 4 6 -- -- 0.4 -- 100 100 -- 100 100 -- 15 8 tcyc + 15 8 Max -- -- -- -- -- -- -- 1.5 1.5 0.6 100 -- -- 100 -- -- 17 -- -- -- -- ns 23.52 tscyc ns 23.51 23.49 * 23.50 Pcyc 23.51 23.50 s Pcyc Unit ns Figure 23.47 23.48 Oscillation settling time SCI Input clock cycle Input clock rise time Input clock fall time Input clock pulse width Transmission data delay time Receive data setup time (clock synchronization) Receive data hold time (clock synchronization) RTS delay time CTS setup time (clock synchronization) CTS hold time (clock synchronization) Port Output data delay time Input data setup time Input data hold time Input data setup time Input data hold time Input data setup time Input data hold time DMAC DREQ setup time DREQ hold time DRAK delay time Note: * Pcyc is the P clock cycle. 3 x tcyc -- + 15 8 6 4 -- -- -- -- 10 23.54 ns 23.53 Rev. 5.00, 09/03, page 706 of 760 CKIO tTCLKS TCLK (input) Figure 23.47 TCLK Input Timing tTCKS CKIO tTCKS TCLK (input) tTCKWL tTCKWH Figure 23.48 TCLK Clock Input Timing Stable oscillation RTC crystal oscillator VCC VCCmin tROSC Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on tSCKW SCK (input) tSCKR tSCKF tSCYC Figure 23.50 SCK Input Clock Timing Rev. 5.00, 09/03, page 707 of 760 tSCYC SCK tTXD TxD (data transmissiion) RxD (data reception) RTS tCTSS CTS tCTSH tRXS tRXH tRTSD Figure 23.51 SCI I/O Timing in Clock Synchronous Mode CKIO tPORTS1 tPORTH1 PORT 7 to 0 (read) (B:P clock ratio = 1:1) PORT 7 to 0 (read) (B:P clock ratio = 2:1) PORT 7 to 0 (read) (B:P clock ratio = 4:1) PORT 7 to 0 (write) tPORTS2 tPORTH2 tPORTS3 tPORTH3 tPORTD Figure 23.52 I/O Port Timing CKIO tDREQS DREQn tDREQH Figure 23.53 DREQ Input Timing Rev. 5.00, 09/03, page 708 of 760 CKIO tDRAKD DRAK0/1 tDRAKD Figure 23.54 DRAK Output Timing 23.3.9 UDI-Related Pin Timing Table 23.9 UDI-Related Pin Timing VccQ = 3.3 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3V, Ta = -20 to 75C Item TCK cycle time TCK high pulse width TCK low pulse width TCK rise/fall time TRST setup time TRST hold time TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time ASEMD0 setup time ASEMD0 hold time Symbol tTCKCYC tTCKH tTCKL tTCKf tTRSTS tTRSTH tTDIS tTDIH tTMSS tTMSH tTDOD tASEMDH tASEMDS Min 50 12 12 -- 12 50 10 10 10 10 -- 12 12 Max -- -- -- 4 -- -- -- -- -- -- 16 -- -- Unit ns ns ns ns ns tcyc ns ns ns ns ns ns ns 23.58 23.57 23.56 Figure 23.55 tTCKCYC tTCKH VIH VIH 1/2VccQ VIL VIL tTCKf tTCKL VIH 1/2VccQ tTCKf Note: When clock is input from TCK pin Figure 23.55 TCK Input Timing Rev. 5.00, 09/03, page 709 of 760 RESETP tTRSTS TRST tTRSTH Figure 23.56 TRST Input Timing (Reset Hold) TCK tTCKCYC tTDIS TDI tTMSS TMS tTDOD TDO tTMSH tTDIH Figure 23.57 UDI Data Transfer Timing RESETP tASEMD0S ASEMD0 tASEMD0H Figure 23.58 ASEMD0 Input Timing Rev. 5.00, 09/03, page 710 of 760 23.3.10 AC Characteristics Measurement Conditions * I/O signal reference level: VccQ/2 (VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V) * Input pulse level: Vss to 3.0 V (where RESETP, RESETM, ASEND0, IRLS3 to IRLS0, IRL3 to IRL0, ADTRG, PINT15 to PINT0, TRST, RxD1, CA, NMI, IRQ5-IRQ0, CKIO, and MD5-MD0 are within Vss to Vcc) * Input rise and fall times: 1 ns IOL LSI output pin CL DUT output VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pF: CKIO, RAS, CAS, CS0, CS2-CS6, CE2A, CE2B, BACK 50pF: All other pins 2. IOL and IOH are the values shown in table 23.3. Figure 23.59 Output Load Circuit Rev. 5.00, 09/03, page 711 of 760 23.3.11 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure 23.60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in figure 23.60, the graph will not be a straight line. +3 Delay Time [ns] +2 +1 +0 +0 +10 +20 +30 +40 +50 Load Capacitance [pF] Figure 23.60 Load Capacitance vs. Delay Time Rev. 5.00, 09/03, page 712 of 760 23.4 A/D Converter Characteristics Table 23.10 lists the A/D converter characteristics. Table 23.10 A/D Converter Characteristics VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Resolution Conversion time Analog input capacitance Permissible signal-source (singlesource) impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 15 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 3.0 2.0 2.0 0.5 4.0 Unit bits s pF k LSB LSB LSB LSB LSB 23.5 D/A Converter Characteristics Table 23.11 lists the D/A converter characteristics. Table 23.11 D/A Converter Characteristics VccQ = 3.3 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Resolution Conversion time Absolute accuracy Min 8 -- -- Typ 8 -- 2.5 Max 8 10.0 4.0 Unit bits s LSB 20-pF capacitive load 2-M resistance load Test Conditions Rev. 5.00, 09/03, page 713 of 760 Rev. 5.00, 09/03, page 714 of 760 Appendix A Pin Functions A.1 Pin States Table A.1 shows pin states during resets, power-down states, and the bus-released state. Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State Reset Category Clock Pin EXTAL XTAL CKIO EXTAL2 XTAL2 CAP1, CAP2 System control RESETP RESETM BREQ BACK MD[5:0] CA STATUS[1:0]/PTJ[7:6] Interrupt IRQ[3:0]/IRL[3:0]/ PTH[3:0] IRQ[4]/ PTH[4] NMI IRLS[3:0]/PTF[3:0]/ PINT[11:8] MCS[7:0]/PTC[7:0]/ PINT[7:0] TCK/PTF[4]/PINT[12] TDI/PTF[5]/PINT[13] TMS/PTF[6]/PINT[14] TRST/PTF[7]/PINT[15] IRQOUT Power-On Manual Reset Reset I O* 1 IO* I O -- I I I O I I O 7 V* V* I V V IV IV IV IV O 7 1 Power-Down Standby I 1 O* IO* I O -- I I I O I I *2 OP I I I IZ 2 1 Sleep I 1 O* IO* I O -- I I I O I I 1 Bus Released I 1 O* IO* I O -- I I I L I I 1 I 1 O* IO* I O -- I I I O I I OP I I I I OP* I I I I O 1 *2 OP I I I I 2 *2 OP* I I I I 2 ZH* K* IZ IZ IZ IZ O 10 OP* I I I I O 2 ZP* I I I I O 2 Rev. 5.00, 09/03, page 715 of 760 Reset Category Address bus Data bus Pin A[25:0] D[15:0] D[23:16]/PTA[7:0] D[31:24]/PTB[7:0] Bus control CS0/MCS0 CS[2:4]/PTK[0:2] CS5/CE1A/PTK[3] CS6/CE1B BS/PTK[4] RAS3L/PTJ[0] RAS3U/PTE[2] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTK[6] WE3/DQMUU/ICIOWR/ PTK[7] RD/WR RD CKE/PTK[5] WAIT DMAC DREQ0/PTD[4] DACK0/PTD[5] DRAK0/PTD[1] DREQ1/PTD[6] DACK1/PTD[7] DRAK1/PTD[0] Timer TCLK/PTH[7] Power-On Manual Reset Reset Z Z Z Z H H H H H H V H H H H H H H H H Z V V V V V V V O I 2 IP* IP* 2 Power-Down Standby ZL* 9 Sleep O IO 2 IOP* IOP* 2 Bus Released Z Z 2 ZP* ZP* 2 Z 2 ZK* ZK* 10 ZH* K *10 K*2 ZH ZH* 10 2 ZH* K* ZOK* 3 ZOK* ZOK* 3 ZOK* ZH* 10 ZH* ZH *10 10 10 3 3 10 2 O 2 OP* 2 OP* ZH *10 *2 O 2 OP* OP* 2 Z 2 ZP* ZP* 2 O 2 OP* OP* 2 OP* OP* 2 OP* O O 2 OP* OP* O O 2 OP* I 6 ZI* OP* 2 OP* ZI* 2 OP* OP* ZP 2 6 2 2 2 2 O 2 OP* OP* 2 OP* OP* 2 OP* O O 2 OP* OP* O O 2 OP* I I 2 2 2 Z 2 ZP* ZOP* 3 ZOP* ZOP* 3 ZOP* Z Z 2 ZP* ZP* Z Z 2 OP* Z I 2 3 3 K *2 2 ZH* K* ZH* 10 ZH* OK *2 Z Z 10 ZK* 10 2 ZH* K* Z 2 ZK* ZH* K* 4 IOP* 10 2 2 OP* 2 OP* I 2 OP* 2 OP* 2 OP* I OP* 2 OP* IOP* 4 2 2 OP* 4 IOP* 2 Rev. 5.00, 09/03, page 716 of 760 Reset Category Pin Power-On Manual Reset Reset 6 Z ZI* Z V Z Z V Z Z V V 7 V* OV V V OV V V V 7 V* V O OV V OV I H V V V H H ZO* 2 ZP* ZI *6 6 6 Power-Down Standby Z 2 ZK* ZK* Z ZK* 2 ZK* Z 2 ZK* ZK* 2 ZK* I OK 10 2 ZH* K* ZH* K* 2 OK* Z Z Z IZ 2 OK* ZK* OK OZ OZ Z 2 2 10 2 2 2 2 Sleep IZ* 5 OZ* IOP* 5 IZ* 4 5 Bus Released IZ* 5 OZ* IOP* 5 IZ* 4 5 SCI/Smart card RxD0/SCPT[0] without FIFO TxD0/SCPT[0] SCK0/SCPT[1] SCIF/IrDA with FIFO RxD1/SCPT[2] TxD1/SCPT[2] SCK1/SCPT[3] SCIF with FIFO RxD2/SCPT[4] TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] CTS2/IRQ5/SCPT[7] Port AUDSYNC/PTE[7] CE2B/PTE[5] CE2A/PTE[4] TDO/PTE[0] IOIS16/PTG[7] PTG[5:0] AUDCK/PHT[6] ADTRG/PTH[5] WAKEUP/PTD[3] RESETOUT/PTD[2] AUDATA[3:0]/PTG[3:0] CKIO2/PTG[4] ASEBRKAK/PTG[5] ASEMD0/PTG[6] PTJ[1] PTE[1] PTE[6] PTE[3] PTJ[4] PTJ[5] ZO* 2 ZP* 6 OZ* 4 IOP* IZ* 5 OZ* IOP* 2 OP* I OP *2 2 4 5 5 OZ* 4 IOP* IZ* 5 OZ* IOP* 2 OP* I OP* 2 ZP* 2 2 4 5 5 ZI* 6 ZO* ZP* 2 OP* ZI* 2 OP* OP* 2 OP* OP I I I I 2 OP* 2 6 2 *2 OP* 2 OP* OP I I I I 2 OP* *2 *2 ZP* 2 OP* I I I I ZP* 2 OP* OK OI OI I 2 OP* OK OI OI I 2 OP* OK OI OI I 3 2 OP* 2 OP* OP* 2 OP* OP* 2 OP* 2 2 ZOK* 3 ZOK* ZOK* 3 ZOK* ZOK* 3 ZOK* 3 3 OP* 2 OP* OP* 2 OP* OP* 2 OP* 2 2 2 ZOP* 3 ZOP* ZOP* 3 ZOP* ZOP* 3 ZOP* 3 3 3 Rev. 5.00, 09/03, page 717 of 760 Reset Category Analog I: O: H: L: Z: P: K: V: Pin AN[5:0]/PTL[5:0] AN[6:7]/DA[1:0]/PTL[6:7] Power-On Manual Reset Reset 6 Z ZI* Z 6 ZI* Power-Down Standby Z 11 OZ* Sleep I 8 IO* Bus Released I 8 IO* Input Output High-level output Low-level output High impedance Input or output depending on register setting Input pin is high impedance, output pin holds its state I/O buffer off, pull-up MOS on Notes: 1. Depending on the clock mode (MD2-MD0 setting). 2. K or P when the port function is used. 3. K or P when the port function is used. Z or O when the port function is not used depending on register setting. 4. K or P when the port function is used. I or O when the port function is not used depending on register setting. 5. Depending on register setting. 6. I or O when the port function is used. 7. Input Schmitt buffers of IRQ[5.0] and ADTRG on; other input buffers off. 8. O when DA output is enabled; otherwise I depending on register setting. 9. In standby mode, Z or L depending on register setting. 10. In standby mode, Z or H depending on register setting. 11. O when DA output is enabled; Z otherwise. Rev. 5.00, 09/03, page 718 of 760 A.2 Pin Specifications Table A.2 shows the pin specifications. Table A.2 Pin MD5 MD4, MD3 MD2 to MD0 RAS3L/PTJ[0] PTJ[1] CE2A/PTE[4] CE2B/PTE[5] RXD0/SCPT[0] RXD1/SCPT[2] RXD2/SCPT[4] TXD0/SCPT[0] TXD1/SCPT[2] TXD2/SCPT[4] SCK0/SCPT[1] SCK1/SCPT[3] SCK2/SCPT[5] RTS2/SCPT[6] Pin Specifications Pin No. (FP-208C, FP-208E) 197 196, 195 2, 1, 144 106 107 103 104 171 172 174 164 166 168 165 167 169 170 Pin No. (BP-240A) C6 D6, A7 C2, D2,G19 U18 U19 V17 V16 B13 C13 B12 C15 A14 C14 D15 B14 D14 A13 B17 B16 I/O I I I I/O I/O I/O I/O I I I O O O I/O I/O I/O I/O I/O I/O Function Operating mode pin (endian mode) Operating mode pin (area 0 bus width) Operating mode pin (clock mode) RAS (SDRAM) / I/O port I/O port PCMCIA CE2A / I/O port PCMCIA CE2B / I/O port Serial port 0 data input / input port Serial port 1 data input / input port Serial port 2 data input / input port Serial port 0 data output / output port Serial port 1 data output / output port Serial port 2 data output / output port Serial port 0 clock input/output / I/O port Serial port 1 clock input/output / I/O port Serial port 2 clock input/output / I/O port Serial port 2 transfer request / I/O port Processor state / I/O port Processor state / I/O port STATUS1/PTJ[7] 158 STATUS0/PTJ[6] 157 Rev. 5.00, 09/03, page 719 of 760 Pin A25 to A0 Pin No. (FP-208C, FP-208E) 86, 84, 82, 80, 78 to 72, 70, 68 to 60, 58, 56 to 53 Pin No. (BP-240A) V12, T12, V11, W10, V10, U9, T9, V9, W9, T8, U8, W8, U7, V7, W7, T6, U6, V6, W6, T5, U5, W5, W4, V5, V3, V4 F4, G1, G2, G3, G4, H1, H3, J1 J2, J4, J3, K2, K1, L2, L1, M4 M2, N4, N3, N2, N1, P4, P3, P2, P1, R4, T4, T3, T1, R2, U2,T2 B11, D11, C11, B10, D9, B9, A9, D8 D10 C9 C8 B8 A8 D7 C4, A5, D4, C5, D5, A6 B3, B5 V15 W16 U16 W15 I/O O Address bus Function D31 to D24/ PTB[7] to PTB[0] D23 to D16/ PTA[7] to PTA[0] D15 to D0 13 to 18, 20, 22 23 to 26, 28, 30 to 32 34, 36 to 44, 46, 48 to 52 I/O Data bus / I/O port I/O I/O Data bus / I/O port Data bus MCS[7:0]/ PTC[7:0]/ PINT[7:0] RESETOUT/ PTD[2] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] AN[5:0]/PTL[5:0] AN[7:6]/DA[1:0]/ PTL[7:6] CS6/CE1B CS5/CE1A/ PTK[3] CS4/PTK[2] CS3/PTK[1] 177 to 180,185 to 188 184 189 190 191 192 204 to 199 207, 206 102 101 100 99 I/O Mask ROM chip select / I/O port / port interrupt request Wakeup / I/O port Reset output / I/O port DMA control pin / I/O port DMA control pin / I/O port DMA transfer request 0 / input port DMA transfer request 1 / input port Analog input pin / input port Analog I/O pin / input port Chip select 6 / PCMCIA CE1B Chip select 5 / PCMCIA CE2B / I/O port Chip select 4 / I/O port Chip select 3 / I/O port WAKEUP/PTD[3] 182 I/O I/O I/O I/O I I I I/O O I/O I/O I/O Rev. 5.00, 09/03, page 720 of 760 Pin CS2/PTK[0] CS0/MCS0 BS/PTK[4] PTJ[5] PTJ[4] CASU/PTJ[3] CASL/PTJ[2] DACK0/PTD[5] DACK1/PTD[7] RD WE0/ DQMLL Pin No. (FP-208C, FP-208E) 98 96 87 113 112 110 108 114 115 88 89 Pin No. (BP-240A) T16 T15 W12 R17 U17 T17 R18 R16 P19 T13 U13 V13 I/O I/O O I/O I/O I/O I/O I/O I/O I/O O O O Function Chip select 2 / I/O port Chip select 0 / Mask ROM chip select 0 Bus cycle start / I/O port I/O port I/O port CAS(SDRAM) / I/O port CAS(SDRAM) / I/O port DMA transfer strobe 0 / I/O port DMA transfer strobe 1 / I/O port Read strobe pin D7-D0 select signal/ DQM(SDRAM) D15-D8 select signal / DQM(SDRAM)/ PCMCIA WE signal D23-D16 select signal / DQM(SDRAM) / PCMCIA IORD signal / I/O port D31-D24 select signal /DQM(SDRAM) / PCMCIA IOWR signal / I/O port Read/write select signal AUD synchronous I/O port I/O port I/O port RAS(SDRAM) / I/O port I/O port Test data output I/O port Manual reset input ADC trigger request / Input port I/O for PC card / input port ASE mode / input port ASE break accept / input port WE1/DQMLU/WE 90 WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] RD/WR AUDSYNC/ PTE[7] PTE[6] PTE[3] RAS3U/PTE[2] PTE[1] TDO/PTE[0] RESETM ADTRG/PTH[5] IOIS16/PTG[7] ASMD0/PTG[6] ASEBRKAK/ PTG[5] 91 W13 I/O 92 T14 I/O 93 94 116 117 118 119 120 124 125 126 127 128 U14 V14 P18 P17 P16 N19 N18 M18 M17 M16 L19 L18 O I/O I/O I/O I/O I/O I/O I I I I I Rev. 5.00, 09/03, page 721 of 760 Pin CKIO2/PTG[4] AUDATA[3]/ PTG[3] AUDATA[2]/ PTG[2] AUDATA[1]/ PTG[1] AUDATA[0]/ PTG[0] TRST/PTF[7]/ PINT[15] TMS/PTF[6]/ PINT[14] TDI/PTF[5]/ PINT[13] TCK/PTF[4]/ PINT[12] IRLS[3:0]/ PTF[3:0]/ PINT[11:8] AUDCK/PTH[6] WAIT BREQ BACK IRQOUT RESETP NMI Pin No. (FP-208C, FP-208E) 129 130 131 133 135 136 137 138 139 140 to 143 Pin No. (BP-240A) L16 L17 K18 K19 J18 J19 H16 H17 H18 H19, G16, G17, G18 D16 M19 N16 N17 A16 C7 C3 F2, F1, E4, E3 F3 A11 B15 D18 C18 F17 E16 I/O I/O I I I I I I I I I Function System clock output / input port AUD data / input port AUD data / input port AUD data / input port AUD data / input port Test reset / input port / port interrupt request Test mode switch / input port / port interrupt request Test data input / input port / port interrupt request Test clock / input port / port interrupt request External interrupt request / input port / port interrupt request AUD clock / input port Hardware wait request Bus request Bus acknowledge Interrupt / refresh request output Power-on reset input Nonmaskable interrupt request External interrupt request / external interrupt source / input port External interrupt request / input port Serial port 2 transfer enable / external interrupt request / input port Clock I/O (for TMU/RTC) / I/O port External clock / crystal oscillator pin Crystal oscillator pin External capacitance pin (for PLL1) External capacitance pin (for PLL2) 151 123 122 121 160 193 7 I I I O O I I I I I I/O I O -- -- IRQ[3:0]/IRL[3:0]/ 11 to 8 PTH[3:0] IRQ4/PTH[4] CTS2/IRQ5/ SCPT[7] TCLK/PTH[7] EXTAL XTAL CAP1 CAP2 12 176 159 156 155 146 149 Rev. 5.00, 09/03, page 722 of 760 Pin CKIO XTAL2 EXTAL2 CKE/PTK[5] CA VCCQ Pin No. (FP-208C, FP-208E) 162 4 5 105 194 21, 35, 47, 59, 71, 85, 97, 111, 163, 183 3 145 150 205 19, 33, 45, 57, 69, 83, 95, 109, 161, 181 29, 81, 134, 154, 175 Pin No. (BP-240A) A15 D1 D3 T18 B7 H4, M1, R1, U3, V8, U15, R19, C17, A10, U12 E2 F16, E17 A4 H2, M3, R3, T7, U4, W11, W14, T19, C16, C10 L3, L4, U11, T11, J17, J16, E18, C19, C12, D12 I/O I/O O I I/O I Function System clock I/O Crystal oscillator pin (for on-chip RTC) Crystal oscillator pin (for on-chip RTC) CK enable for SDRAM / I/O port Setting hardware standby pin Power Power supply (3.3 V) supply VCC-RTC VCC-PLL1 VCC-PLL2 AVCC VSSQ Power RTC oscillator power supply supply (2.0/1.9/1.8/1.7 V) Power PLL power supply (2.0/1.9/1.8/1.7 V) supply Power Analog power supply (3.3 V) supply Power Power supply (0 V) supply VCC Power Internal power supply supply (2.0/1.9/1.8/1.7 V) VSS 27, 79, 132, K3, K4, U10, 152, 153, 173 T10, K17, K16, E19, D17, D19, A12, D13 6 147 148 198, 208 E1 F18 F19 B6, B4 Power Internal power supply (0 V) supply VSS-RTC VSS-PLL1 VSS-PLL2 AVSS Power RTC-oscillator power supply (0 V) supply Power PLL power supply (0 V) supply Power Analog power supply (0 V) supply Note: Except in hardware standby mode, power must be supplied constantly to all power supply pins. In hardware standby mode, power must be supplied to Vcc-RTC and Vss-RTC at least. Rev. 5.00, 09/03, page 723 of 760 A.3 Treatment of Unused Pins Pull up (2.0/1.9/1.8/1.7 V) Leave unconnected Power supply (2.0/1.9/1.8/1.7 V) Power supply (0 V) Leave unconnected Power supply (0 V) Leave unconnected Pull up (3.3 V) Leave unconnected Power supply (3.3 V) Power supply (0 V) Pull up (3.3 V) * When RTC is not used EXTAL2: XTAL2: VCC-RTC: VSS-RTC: CAP2: VSS-PLL2: XTAL: EXTAL: AN[7:0]: AVCC: AVSS: ASEMD0: * When PLL2 is not used VCC-PLL2: Power supply (2.0/1.9/1.8/1.7 V) * When on-chip crystal oscillator is not used * When EXTAL pin is not used * When A/D converter is not used * When UDI is not used Rev. 5.00, 09/03, page 724 of 760 A.4 Pin States in Access to Each Address Space Pin States (Ordinary Memory/Little Endian) Pin 8-Bit Bus Width Byte/Word/Longword Access Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 Word/Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 Table A.3 CS6 to CS2, CS0 RD RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R R R R R R Enabled Low High Enabled High High High High High High High High High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 W Low W High W High W High W High W Low Rev. 5.00, 09/03, page 725 of 760 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Enabled R R Low High Enabled High High High High R R R R High High High High High High Disabled Disabled Address Valid data Invalid data Invalid data Invalid data W Low WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W High W High W High W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL W Low Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Disabled Address Invalid data Valid data Invalid data Invalid data Enabled Low High High Low Enabled High High High High High High High High High Low High High High High Disabled Disabled Address Invalid data Invalid data Valid data Invalid data Enabled Low High High Low Enabled High High High High High High High High High High High Low High High Disabled Disabled Address Invalid data Invalid data Invalid data Valid data Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Disabled Address Valid data Valid data Invalid data Invalid data Enabled Low High High Low Enabled High High High High High High High High High Low High Low High High Disabled Disabled Address Invalid data Invalid data Valid data Valid data Enabled Low High High Low Enabled High High High High High Low High Low High Low High Low High High Disabled Disabled Address Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 726 of 760 Table A.4 Pin States (Ordinary Memory/Big Endian) 8-Bit Bus Width Pin Byte/Word/Longword Access Enabled R Low Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 Word/Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R R High W Low Enabled High High High High High W Low R High W High R High W High R High W High High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00, 09/03, page 727 of 760 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Enabled R R Low High Enabled High High High High R R R R High High High High High High Disabled Disabled Address Invalid data Invalid data Invalid data Valid data W High WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W High W High W Low W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL W Low Enabled Low High High Low Enabled High High High High High High High High High Low High High High High Disabled Disabled Address Invalid data Invalid data Valid data Invalid data Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Disabled Address Invalid data Valid data Invalid data Invalid data Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Disabled Address Valid data Invalid data Invalid data Invalid data Enabled Low High High Low Enabled High High High High High High High High High Low High Low High High Disabled Disabled Address Invalid data Invalid data Valid data Valid data Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Disabled Address Valid data Valid data Invalid data Invalid data Enabled Low High High Low Enabled High High High High High Low High Low High Low High Low High High Disabled Disabled Address Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 728 of 760 Table A.5 Pin States (Burst ROM/Little Endian) 8-Bit Bus Width Pin Byte/Word/Longword Access Enabled R Low Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 Word/Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD W-- RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R R High W-- Enabled High High High High High W-- R High W-- R High W-- R High W-- High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00, 09/03, page 729 of 760 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Enabled R R Low High Enabled High High High High R R R R High High High High High High Disabled Disabled Address Valid data Invalid data Invalid data Invalid data W-- WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W-- W-- W-- W-- RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL W-- Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Valid data Invalid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Valid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Invalid data Valid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Valid data Invalid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Valid data Valid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 730 of 760 Table A.6 Pin States (Burst ROM/Big Endian) 8-Bit Bus Width Pin Byte/Word/Longword Access Enabled R Low Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 Word/Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD W-- RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R R High W-- Enabled High High High High High W-- R High W-- R High W-- R High W-- High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00, 09/03, page 731 of 760 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Longword Access Access Access (Address (Address (Address (Address (Address (Address Access 4n) 4n + 1) 4n + 2) 4n + 3) 4n) 4n + 2) Enabled R R Low High Enabled High High High High R R R R High High High High High High Disabled Disabled Address Invalid data Invalid data Invalid data Valid data W-- WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W-- W-- W-- W-- RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL W-- Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Valid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Valid data Invalid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Invalid data Invalid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Valid data Valid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Valid data Invalid data Invalid data Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 732 of 760 Table A.7 Pin States (Synchronous DRAM/Little Endian) 32-Bit Bus Width Pin Byte Access (Address 4n) Enabled R R High High Enabled High/Low*1 Low/High*1 Low High R R R R Low High High High High High High*2 Disabled Disabled Address command Valid data Invalid data Invalid data Invalid data W Low W High Byte Access (Address 4n + 1) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High Low Low High High High High High High High*2 Disabled Disabled Address command Invalid data Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High High High Low Low High High High High High*2 Disabled Disabled Address command Invalid data Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High High High High High Low Low High High High*2 Disabled Disabled Address command Invalid data Invalid data Invalid data Valid data Word Access (Address 4n) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High Low Low Low Low High High High High High High High*2 Disabled Disabled Address command Valid data Valid data Invalid data Invalid data Word Access Longword Access (Address 4n + 2) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High High High Low Low Low Low High High High*2 Disabled Disabled Address command Invalid data Invalid data Valid data Valid data Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High Low Low Low Low Low Low Low Low High High High*2 Disabled Disabled Address command Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W Low W High W High W High Notes: 1. Lower 32-MB access/ Upper 32-MB access/64-MB access 2. Normally high. Low in self-refreshing. Rev. 5.00, 09/03, page 733 of 760 Table A.8 Pin States (Synchronous DRAM/Big Endian) 32-Bit Bus Width Pin Byte Access (Address 4n) Enabled R R High High Enabled High/Low*1 Low/High*1 Low High R R R R High High High Low High High High*2 Disabled Disabled Address command Invalid data Invalid data Invalid data Valid data W High W High Byte Access (Address 4n + 1) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High High High Low Low High High High High High*2 Disabled Disabled Address command Invalid data Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High Low Low High High High High High High High*2 Disabled Disabled Address command Invalid data Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High Low Low High High High High High High High High High*2 Disabled Disabled Address command Valid data Invalid data Invalid data Invalid data Word Access (Address 4n) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High High High High High Low Low Low Low High High High*2 Disabled Disabled Address command Invalid data Invalid data Valid data Valid data Word Access Longword (Address Access 4n + 2) Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High Low Low Low Low High High High High High High High*2 Disabled Disabled Address command Valid data Valid data Invalid data Invalid data Enabled High High High Low Enabled High/Low*1 Low/High*1 Low High Low Low Low Low Low Low Low Low High High High*2 Disabled Disabled Address command Valid data Valid data Valid data Valid data CS6 to CS2, CS0 RD RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 W Low W High W High W Low Notes: 1. Lower 32-MB access/ Upper 32-MB access/64-MB access 2. Normally high. Low in self-refreshing. Rev. 5.00, 09/03, page 734 of 760 Table A.9 Pin States (PCMCIA/Little Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High Low High PCMCIA/IO Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Byte Access (Address 2n + 1) High High High High Low Enabled High High High High High High High High Low High High Low Low High Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low Low High Pin Byte/ Word/ Longword Access Enabled R Low W High R High W Low Enabled High High High High R High W High R High W Low R High W High R High W High High High Byte/ Word/ Word/ LongLongword word Ac Access cess Enabled Low High High Low Enabled High High High High High High High Low High High High High Low High Enabled High High High Low Enabled High High High High High High High High Low High High Low High High CS6 to CS2, CS0 RD RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Disabled Disabled Disabled Disabled Disabled Enabled Address Valid data High-Z*2 High-Z*2 Address Valid data Invalid data High-Z*2 Address Invalid data Valid data High-Z*2 Address Valid data Valid data High-Z*2 Address Valid data High-Z*2 High-Z*2 Address Valid data Invalid data High-Z*2 Address Invalid data Valid data High-Z*2 Enabled Address Valid data Valid data High-Z*2 Rev. 5.00, 09/03, page 735 of 760 PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Pin Byte/ Word/ Longword Access Enabled R Low W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R High W Low Enabled High High High High R High W High R High W Low R High W High R High W High High High 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High High Low Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High High High Low PCMCIA/IO Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High High High Low High High Low High Low Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High Low CS6 to CS2, CS0 RD Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Disabled Disabled Disabled Disabled Disabled Enabled Address Valid data High-Z*2 High-Z*2 Address Valid data Invalid data High-Z*2 Address Invalid data Valid data High-Z*2 Address Valid data Valid data High-Z*2 Address Valid data High-Z*2 High-Z*2 Address Valid data Invalid data High-Z*2 Address Invalid data Valid data High-Z*2 Enabled Address Valid data Valid data High-Z*2 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 736 of 760 Table A.10 Pin States (PCMCIA/Big Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width Pin Byte/ Word/ Longword Access Enabled R Low W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R High W Low Enabled High High High High R High W High R High W Low R High W High R High W High High High 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High Low High Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High High Low High PCMCIA I/O Interface (Area 5) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Byte Access (Address 2n + 1) High High High High Low Enabled High High High High High High High High Low High High Low Low High Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low Low High CS6 to CS2, CS0 RD Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Address Valid data High-Z*2 High-Z*2 Address Invalid data Address Valid data Address Valid data Valid data High-Z*2 Address Valid data High-Z*2 High-Z*2 Address Invalid data Valid data High-Z*2 Address Valid data Invalid data High-Z*2 Address Valid data Valid data High-Z*2 Valid data Invalid data High-Z*2 High-Z*2 Rev. 5.00, 09/03, page 737 of 760 PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Pin Byte/ Word/ Longword Access Enabled R Low W High RD/WR BS RAS3U/PTE[2] RAS3L/PTJ[0] CASL/PTJ[2] CASU/PTJ[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] WAIT IOIS16/PTG[7] A25 to A0 D7 to D0 D15 to D8 D31 to D16 R High W Low Enabled High High High High R High W High R High W Low R High W High R High W High High High 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High High Low PCMCIA/IO Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High High High Low High High Low High Low Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High High High Low Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High Low CS6 to CS2, CS0 RD Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Disabled Disabled Disabled Disabled Disabled Enabled Address Valid data High-Z*2 High-Z*2 Address Invalid data Valid data High-Z*2 Address Valid data Invalid data High-Z*2 Address Valid data Valid data High-Z*2 Address Valid data High-Z*2 High-Z*2 Address Invalid data Valid data High-Z*2 Address Valid data Invalid data High-Z*2 Enabled Address Valid data Valid data High-Z*2 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up. Rev. 5.00, 09/03, page 738 of 760 Appendix B Memory-Mapped Control Registers B.1 Register Address Map Memory-Mapped Control Registers Module* CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC CPG CPG CPG CPG 1 Table B.1 Control Register PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR CCR2 TRA EXPEVT INTEVT BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR FRQCR STBCR STBCR2 WTCNT Bus* L L L L L L L L I L L L L L L L L L L L L L L L I I I I 2 Address* FFFFFFF0 FFFFFFF4 FFFFFFF8 FFFFFFFC FFFFFFE0 FFFFFFE4 FFFFFFE8 FFFFFFEC 40000B0 FFFFFFD0 FFFFFFD4 FFFFFFD8 FFFFFFB0 FFFFFFB4 FFFFFFB8 FFFFFFA0 FFFFFFA4 FFFFFFA8 FFFFFF90 FFFFFF94 FFFFFF98 FFFFFF9C FFFFFFAC FFFFFFBC FFFFFF80 FFFFFF82 FFFFFF88 FFFFFF84 4 Size (Bits) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 32 32 16 32 32 16 16 32 32 16 8 8 8 Access Size (Bits)3. 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 32 32 16 32 32 16 16 32 32 16 8 8 16 Rev. 5.00, 09/03, page 739 of 760 Control Register WTCSR BCR1 BCR2 WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR MCSCR0 MCSCR1 MCSCR2 MCSCR3 MCSCR4 MCSCR5 MCSCR6 MCSCR7 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR Module* CPG BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC 1 Bus* I I I I I I I I I I I I I I I I I I I I P P P P P P P P P P P 2 Address* FFFFFF86 FFFFFF60 FFFFFF62 FFFFFF64 FFFFFF66 FFFFFF68 FFFFFF6C FFFFFF6E FFFFFF70 FFFFFF72 FFFFFF74 FFFFD000- FFFFEFFF FFFFFF50 FFFFFF52 FFFFFF54 FFFFFF56 FFFFFF58 FFFFFF5A FFFFFF5C FFFFFF5E FFFFFEC0 FFFFFEC2 FFFFFEC4 FFFFFEC6 FFFFFEC8 FFFFFECA FFFFFECC FFFFFECE FFFFFED0 FFFFFED2 FFFFFED4 4 Size (Bits) 8 16 16 16 16 16 16 16 16 16 16 -- 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 Access Size (Bits)* 16 16 16 16 16 16 16 16 16 16 16 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 3 Rev. 5.00, 09/03, page 740 of 760 Control Register RWKAR RDAYAR RMONAR RCR1 RCR2 ICR0 IPRA IPRB TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR INTEVT2 IRR0 IRR1 IRR2 Module* RTC RTC RTC RTC RTC INTC INTC INTC TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU SCI SCI SCI SCI SCI SCI SCI INTC INTC INTC INTC 1 Bus* P P P P P I I I P P P P P P P P P P P P P P P P P P P I I I I 2 Address* FFFFFED6 FFFFFED8 FFFFFEDA FFFFFEDC FFFFFEDE FFFFFEE0 FFFFFEE2 FFFFFEE4 FFFFFE90 FFFFFE92 FFFFFE94 FFFFFE98 FFFFFE9C FFFFFEA0 FFFFFEA4 FFFFFEA8 FFFFFEAC FFFFFEB0 FFFFFEB4 FFFFFEB8 FFFFFE80 FFFFFE82 FFFFFE84 FFFFFE86 FFFFFE88 FFFFFE8A FFFFFE8C 4000000 4000004 4000006 4000008 4 Size (Bits) 8 8 8 8 8 16 16 16 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8 32 16 16 16 Access Size (Bits)* 8 8 8 8 8 16 16 16 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8 32 8 8 8 3 Rev. 5.00, 09/03, page 741 of 760 Control Register ICR1 ICR2 PINTER IPRC IPRD IPRE SAR0 DAR0 DMATCR0 CHCR0 SAR1 DAR1 DMATCR1 CHCR1 SAR2 DAR2 DMATCR2 CHCR2 SAR3 DAR3 DMATCR3 CHCR3 DMAOR CMSTR CMCSR CMCNT CMCOR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH Module* INTC INTC INTC INTC INTC INTC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC CMT CMT CMT CMT A/D A/D A/D A/D A/D 1 Bus* I I I I I I P P P P P P P P P P P P P P P P P P P P P P P P P P 2 Address* 4000010 4000012 4000014 4000016 4000018 400001A 4000020 4000024 4000028 400002C 4000030 4000034 4000038 400003C 4000040 4000044 4000048 400004C 4000050 4000054 4000058 400005C 4000060 4000070 4000072 4000074 4000076 4000080 4000082 4000084 4000086 4000088 4 Size (Bits) 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 8 8 8 8 8 Access Size (Bits)* 16 16 16 16 16 16 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 8,16 8,16,32 8,16,32 8,16,32 8,16,32 56 8,16,32* * 5 8,16* 56 8,16,32* * 5 8,16* 56 8,16,32* * 3 Rev. 5.00, 09/03, page 742 of 760 Control Register ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PLCR SCPCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR PLDR SCPDR Module* A/D A/D A/D A/D A/D D/A D/A D/A PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT 1 Bus* P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P 2 Address* 400008A 400008C 400008E 4000090 4000092 40000A0 40000A2 40000A4 4000100 4000102 4000104 4000106 4000108 400010A 400010C 400010E 4000110 4000112 4000114 4000116 4000120 4000122 4000124 4000126 4000128 400012A 400012C 400012E 4000130 4000132 4000134 4000136 4 Size (Bits) 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 Access Size (Bits)* 5 8,16* 56 8,16,32* * 5 8,16* 56 8,16,32* * 3 8,16 56 8,16,32* * 5 8,16* 8,16,32 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 5.00, 09/03, page 743 of 760 Control Register SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCSSR1 SCFRDR1 SCFCR1 SCFDR1 SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 SCFRDR2 SCFCR2 SCFDR2 SDIR Module* IrDA IrDA IrDA IrDA IrDA IrDA IrDA IrDA SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF UDI 1 Bus* P P P P P P P P P P P P P P P P I 2 Address* 4000140 4000142 4000144 4000146 4000148 400014A 400014C 400014E 4000150 4000152 4000154 4000156 4000158 400015A 400015C 400015E 4000200 4 Size (Bits) 8 8 8 8 16 8 8 16 8 8 8 8 16 8 8 16 16 Access Size (Bits)* 8 8 8 8 16 8 8 16 8 8 8 8 16 8 8 16 16 3 Notes: 1. Modules: CCN: Cache controller UBC: User break controller CPG: Clock pulse generator BSC: Bus state controller RTC: Realtime clock INTC: Interrupt controller TMU: Timer unit SCI: Serial communication interface 2. Internal buses: L: CPU, CCN, cache, TLB connected I: BSC, cache, DMAC, INTC, CPG, and UDI connected P: BSC and peripheral modules (RTC, TMU, SCI, SCIF, IrDA, A/D, D/A, DMAC, PORT, CMT) connected 3. The access size shown is for control register access (read/write). An incorrect result will be obtained if a different size from that shown is used for access. 4. To exclude area 1 control registers from address translation by the MMU, set the first 3 bits of the logical address to 101, to locate the registers in the P2 space. 5. With 16-bit access, it is not possible to read data in two registers simultaneously. 6. With 32-bit access, it is possible to read data in the register at [accessed address + 2] simultaneously. Rev. 5.00, 09/03, page 744 of 760 B.2 Register Bits Register Bits Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 Bit 2 Bit 1 Bit 0 Module BSC Table B.2 Register SDMR SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR TOCR TSTR TCOR0 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI SCI TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI SCI TDRE RDRF ORER FER PER TEND MPB MPBT SCI SCI -- -- -- -- -- -- -- -- -- -- -- -- SDIR -- -- SINV -- STR2 -- -- STR1 SMIF TCOE STR0 SCI TMU TMU TMU TCNT0 TMU TCR0 -- -- -- -- -- UNIE -- CKEG1 -- CKEG0 -- TPSC2 -- TPSC1 UNF TPSC0 TMU TCOR1 TMU TCNT1 TMU Rev. 5.00, 09/03, page 745 of 760 Register TCR1 Bit 7 -- -- Bit 6 -- -- Bit 5 -- UNIE Bit 4 -- CKEG1 Bit 3 -- CKEG0 Bit 2 -- TPSC2 Bit 1 -- TPSC1 Bit 0 UNF TPSC0 Module TMU TCOR2 TMU TCNT2 TMU TCR2 -- ICPE1 -- ICPE0 -- UNIE -- CKEG1 -- CKEG0 -- TPSC2 ICPF TPSC1 UNF TPSC0 TMU TCPR2 TMU R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RWKAR RHRAR RDAYAR RMONAR -- -- -- -- -- -- -- -- -- 1 Hz 2 Hz 10 sec 10 min 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC 1 sec 1 min 1 hour -- Day of week 1 day 1 month 1 year 1 sec 1 min -- -- Day of week 1 hour 1 day 1 month -- -- 10 hours -- 10 days -- 10 months -- 10 years ENB ENB ENB ENB ENB ENB -- -- -- -- -- 10 sec 10 min -- 10 hours 10 days 10 months Rev. 5.00, 09/03, page 746 of 760 Register RCR1 RCR2 ICR0 Bit 7 CF PEF NML -- Bit 6 -- PES2 -- -- Bit 5 -- PES1 -- -- Bit 4 CIE PES0 -- -- Bit 3 AIE RTCEN -- -- Bit 2 -- ADJ -- -- Bit 1 -- RESET -- -- Bit 0 AF START NMIE -- Module RTC RTC INTC IPRA TMU0 TMU2 TMU1 RTC REF -- -- -- -- INTC IPRB WDT SCI INTC BCR1 PULA PULD HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 A6PCM A4SZ0 -- A4IW0 A0IW0 A4W1 A0W0 TRAS0 -- BSC A5BST0 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 A5PCM BCR2 -- A3SZ1 WCR1 WAITSEL -- A3SZ0 -- A3IW0 A6W1 A3W1 TPC0 AMX3 A5W3 A6SZ1 A2SZ1 A6IW1 A2IW1 A6W0 A3W0 RCD1 AMX2 -- A6SZ0 A2SZ0 A6IW0 A2IW0 A5W2 A2W1 RCD0 AMX1 -- A5SZ1 -- A5IW1 -- A5W1 A2W0 TRWL1 AMX0 A5SZ0 -- A5IW0 -- A5W0 A0W2 TRWL0 RFSH A4SZ1 -- A4IW1 A0IW1 A4W2 A0W1 TRAS1 RMODE BSC BSC A3IW1 WCR2 A6W2 A4W0 MCR TPC1 RASD PCR A6W3 BSC BSC A5TED2 A6TED2 A5TEH2 A6TEH2 BSC A5TED1 A5TED0 A6TED1 A6TED0 A5TEH1 A5TEH0 A6TEH1 A6TEH0 RTCSR -- CMF RTCNT -- -- CMIE -- -- CKS2 -- -- CKS1 -- -- CKS0 -- -- OVF -- -- OVIE -- -- LMTS -- BSC BSC RTCOR -- -- -- -- -- -- -- -- BSC Rev. 5.00, 09/03, page 747 of 760 Register RFCR Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 -- Bit 0 -- Module BSC FRQCR STC2 PLLEN IFC2 PSTBY -- MDCHG PFC2 STC1 -- MSTP8 -- STC0 STBXTL MSTP7 -- IFC1 -- -- IFC0 SLPFRQ CKOEN PFC0 MSTP0 MSTP3 CPG PFC1 STBCR STBCR2 WTCNT WTCSR BDRB STBY MSTP9 MSTP2 MSTP1 CPG CPG CPG MSTP6 MSTP5 MSTP4 TME WT/IT RSTS WOVF IOVF CKS2 CKS1 CKS0 CPG UBC BDMRB UBC BRCR -- -- SCMFCA DBEB -- -- SCMFCB PCBB -- BASMA -- BASMB -- -- PCTE SEQ -- -- PCBA -- -- -- -- -- -- -- -- ETBE UBC SCMFDA SCMFDB -- -- BARB UBC BAMRB BBRB -- -- CDB1 -- -- CDB0 -- -- IDB1 -- -- IDB0 -- -- RWB1 BASM -- RWB0 BAM -- SZB1 BAM -- SZB0 UBC UBC BARA UBC Rev. 5.00, 09/03, page 748 of 760 Register BAMRA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module UBC BBRA -- CDA1 -- CDA0 -- -- IDA1 -- -- IDA0 -- -- RWA1 -- RWA0 -- SZA1 -- SZA0 UBC BETR -- UBC BRSR SVF BSA23 BSA15 BSA7 PID2 BSA22 BSA14 BSA6 -- BDA22 BDA14 BDA6 -- -- -- PID1 BSA21 BSA13 BSA5 -- BDA21 BDA13 BDA5 -- -- -- PID0 BSA20 BSA12 BSA4 -- BDA20 BDA12 BDA4 -- -- -- BSA27 BSA19 BSA11 BSA3 BDA27 BDA19 BDA11 BDA3 -- -- -- BSA26 BSA18 BSA10 BSA2 BDA26 BDA18 BDA10 BDA2 -- -- -- BSA25 BSA17 BSA9 BSA1 BDA25 BDA17 BDA9 BDA1 -- -- BSA24 BSA16 BSA8 BSA0 BDA24 BDA16 BDA8 BDA0 -- -- UBC BRDR DVF BDA23 BDA15 BDA7 UBC TRA -- -- -- CCN -- EXPEVT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCN INTEVT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCN MMUCR -- -- -- -- -- -- -- -- -- -- -- RC -- -- -- RC -- -- -- -- -- -- -- TF -- -- -- IX -- -- SV AT CCN Rev. 5.00, 09/03, page 749 of 760 Register BASRA BASRB CCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module UBC UBC -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- 0 -- -- -- CF -- -- -- CB -- -- -- WT -- -- -- CE CCN CDR2 CCN W3LOAD W2LOAD PTEH W3LOCK W2LOCK CCN -- -- PTEL CCN -- -- TTB PR PR SZ C D SH V -- CCN TEA CCN INTEVT2 INTC Rev. 5.00, 09/03, page 750 of 760 Register IRR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC PINT0R IRR1 TXI1R IRR2 -- ICR1 MAI IRQ31S ICR2 PINT1R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R INTC BRI1R RXI1R ERI1R DEI3R DEI2R DEI1R DEI0R INTC -- IRQLVL IRQ30S -- BLMSK IRQ21S ADIR -- IRQ20S TXI2R IRQ51S IRQ11S BRI2R IRQ50S IRQ10S RXI2R IRQ41S IRQ01S ERI2R IRQ40S IRQ00S PINT8S PINT0S PINT8E PINT0E INTC INTC INTC INTC PINT15S PINT14S PINT13S PINT12S PINT11S PINT10S PINT9S PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINTER PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E IPRC IRQ3 level IRQ1 level IRQ2 level IRQ0 level PINT8 to 15 level IRQ4 level IrDA level A/D level IPRD PINT0 to 7 level IRQ5 level INTC IPRE DMAC level SCIF level INTC SAR0 DMAC DAR0 DMAC DMATCR0 -- -- -- -- -- -- -- -- DMAC Rev. 5.00, 09/03, page 751 of 760 Register CHCR0 Bit 7 -- -- DM1 -- Bit 6 -- -- DM0 DS Bit 5 -- -- SM1 TM Bit 4 -- -- SM0 TS1 Bit 3 -- -- RS3 TS0 Bit 2 -- RL RS2 IE Bit 1 -- AM RS1 TE Bit 0 -- AL RS0 DE Module DMAC SAR1 DMAC DAR1 DMAC DMATCR1 -- -- -- -- -- -- -- -- DMAC CHCR1 -- -- DM1 -- -- -- DM0 DS -- -- SM1 TM -- -- SM0 TS1 -- -- RS3 TS0 -- RL RS2 IE -- AM RS1 TE -- AL RS0 DE DMAC SAR2 DMAC DAR2 DMAC DMATCR2 -- -- -- -- -- -- -- -- DMAC Rev. 5.00, 09/03, page 752 of 760 Register CHCR2 Bit 7 -- -- DM1 -- Bit 6 -- -- DM0 -- Bit 5 -- -- SM1 TM Bit 4 -- -- SM0 TS1 Bit 3 -- RO RS3 TS0 Bit 2 -- -- RS2 IE Bit 1 -- -- RS1 TE Bit 0 -- -- RS0 DE Module DMAC SAR3 DMAC DAR3 DMAC DMATCR3 -- -- -- -- -- -- -- -- DMAC CHCR3 -- -- DM1 -- -- -- DM0 -- -- -- -- -- -- -- -- -- SM1 TM -- -- -- -- -- -- -- DI SM0 TS1 -- -- -- -- -- -- -- -- RS3 TS0 -- -- -- -- -- -- -- -- RS2 IE -- AE -- -- -- -- -- -- RS1 TE PR1 NMIF -- -- -- CKS1 -- -- RS0 DE PR0 DME -- STR -- CKS0 DMAC DMAOR -- -- DMAC CMSTR -- -- CMT CMCSR -- CMF CMT CMCNT CMT CMCOR CMT ADDRAH ADDRAL AD9 AD1 AD8 AD0 AD7 -- AD6 -- AD5 -- AD4 -- AD3 -- AD2 -- A/DC A/DC Rev. 5.00, 09/03, page 753 of 760 Register ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR PACR Bit 7 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE1 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 ADE TRGE2 Bit 5 AD7 -- AD7 -- AD7 -- ADST SCN Bit 4 AD6 -- AD6 -- AD6 -- MULT1 Bit 3 AD5 -- AD5 -- AD5 -- CKS Bit 2 AD4 -- AD4 -- AD4 -- CH2 -- Bit 1 AD3 -- AD3 -- AD3 -- CH1 -- Bit 0 AD2 -- AD2 -- AD2 -- CH0 -- Module A/DC A/DC A/DC A/DC A/DC A/DC A/DC A/DC D/AC D/AC RESVD1 RESVD2 DAOE1 PA7M D1 PA3M D1 DAOE0 PA7M D0 PA3M D0 PB7M D0 PB3M D0 PC7M D0 PC3M D0 PD7M D0 PD3M D0 PE7M D0 PE3M D0 PF7M D0 PF3M D0 DAE PA6M D1 PA2M D1 PB6M D1 PB2M D1 PC6M D1 PC2M D1 PD6M D1 PD2M D1 PE6M D1 PE2M D1 PF6M D1 PF2M D1 -- PA6M D0 PA2M D0 PB6M D0 PB2M D0 PC6M D0 PC2M D0 PD6M D0 PD2M D0 PE6M D0 PE2M D0 PF6M D0 PF2M D0 -- PA5M D1 PA1M D1 PB5M D1 PB1M D1 PC5M D1 PC1M D1 PD5M D1 PD1M D1 PE5M D1 PE1M D1 PF5M D1 PF1M D1 -- PA5M D0 PA1M D0 PB5M D0 PB1M D0 PC5M D0 PC1M D0 PD5M D0 PD1M D0 PE5M D0 PE1M D0 PF5M D0 PF1M D0 -- PA4M D1 PA0M D1 PB4M D1 PB0M D1 PC4M D1 PC0M D1 PD4M D1 PD0M D1 PE4M D1 PE0M D1 PF4M D1 PF0M D1 -- PA4M D0 PA0M D0 PB4M D0 PB0M D0 PC4M D0 PC0M D0 PD4M D0 PD0M D0 PE4M D0 PE0M D0 PF4M D0 PF0M D0 D/AC PORT PBCR PB7M D1 PB3M D1 PORT PCDR PC7M D1 PC3M D1 PORT PDCR PD7M D1 PD3M D1 PORT PECR PE7M D1 PE3M D1 PORT PFCR PF7M D1 PF3M D1 PORT Rev. 5.00, 09/03, page 754 of 760 Register PGCR Bit 7 PG7M D1 PG3M D1 Bit 6 PG7M D0 PG3M D0 PH7M D0 PH3M D0 PJ7M D0 PJ3M D0 PK7M D0 PK3M D0 PL7M D0 PL3M D0 SCP7M D0 SCP3M D0 PA6DT PB6DT PC6DT PD6DT PE6DT PF6DT PG6DT PH6DT PJ6DT PK6DT PL6DT Bit 5 PG6M D1 PG2M D1 PH6M D1 PH2M D1 PJ6M D1 PJ2M D1 PK6M D1 PK2M D1 PL6M D1 PL2M D1 SCP6M D1 SCP2M D1 PA5DT PB5DT PC5DT PD5DT PE5DT PF5DT PG5DT PH5DT PJ5DT PK5DT PL5DT Bit 4 PG6M D0 PG2M D0 PH6M D0 PH2M D0 PJ6M D0 PJ2M D0 PK6M D0 PK2M D0 PL6M D0 PL2M D0 SCP6M D0 SCP2M D0 PA4DT PB4DT PC4DT PD4DT PE4DT PF4DT PG4DT PH4DT PJ4DT PK4DT PL4DT Bit 3 PG5M D1 PG1M D1 PH5M D1 PH1M D1 PJ5M D1 PJ1M D1 PK5M D1 PK1M D1 PL5M D1 PL1M D1 SCP5M D1 SCP1M D1 PA3DT PB3DT PC3DT PD3DT PE3DT PF3DT PG3DT PH3DT PJ3DT PK3DT PL3DT Bit 2 PG5M D0 PG1M D0 PH5M D0 PH1M D0 PJ5M D0 PJ1M D0 PK5M D0 PK1M D0 PL5M D0 PL1M D0 SCP5M D0 SCP1M D0 PA2DT PB2DT PC2DT PD2DT PE2DT PF2DT PG2DT PH2DT PJ2DT PK2DT PL2DT Bit 1 PG4M D1 PG0M D1 PH4M D1 PH0M D1 PJ4M D1 PJ0M D1 PK4M D1 PK0M D1 PL4M D1 PL0M D1 SCP4M D1 SCP0M D1 PA1DT PB1DT PC1DT PD1DT PE1DT PF1DT PG1DT PH1DT PJ1DT PK1DT PL1DT Bit 0 PG4M D0 PG0M D0 PH4M D0 PH0M D0 PJ4M D0 PJ0M D0 PK4M D0 PK0M D0 PL4M D0 PL0M D0 SCP4M D0 SCP0M D0 PA0DT PB0DT PC0DT PD0DT PE0DT PF0DT PG0DT PH0DT PJ0DT PK0DT PL0DT Module PORT PHCR PH7M D1 PH3M D1 PORT PJCR PJ7M D1 PJ3M D1 PORT PKCR PK7M D1 PK3M D1 PORT PLCR PL7M D1 PL3M D1 PORT SCPCR SCP7M D1 SCP3M D1 PORT PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR PLDR SCPDR PA7DT PB7DT PC7DT PD7DT PE7DT PF7DT PG7DT PH7DT PJ7DT PK7DT PL7DT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Rev. 5.00, 09/03, page 755 of 760 Register SDIR BIT7 TI3 -- BIT6 TI2 -- ICK3 BIT5 TI1 -- ICK2 BIT4 TI0 -- ICK1 BIT3 -- -- ICK0 BIT2 -- -- PSEL BIT1 -- -- CKS1 BIT0 -- -- CKS0 Module UDI SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCSSR1 IRM0D IrDA IrDA TIE RIE TE RE -- -- CKE1 CKE0 IrDA IrDA PER3 ER PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR IrDA SCFRDR1 SCFCR1 SCFDR1 RTRG1 -- -- SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 PER3 ER SCFRDR2 SCFCR2 SCFDR2 RTRG1 -- -- Legend MMU: UBC: CPG: BSC: RTC: INTC: TMU: SC1: IrDA: SCIF: CCN: DMAC: ADC: DAC: PORT: UDI: RTRG0 -- -- TTRG1 -- -- TTRG0 T4 R4 MCE T3 R3 TFRST T2 R2 RFRST T1 R1 LOOP T0 R0 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR TIE RIE TE RE -- -- CKE1 CKE0 -- RTRG0 -- -- CHR TTRG1 -- -- PE TTRG0 T4 R4 O/E MCE T3 R3 STOP TFRST T2 R2 -- RFRST T1 R1 CKS1 LOOP T0 R0 CKS0 IrDA IrDA IrDA SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF Memory management unit User break controller Clock pulse generator Bus state controller Realtime clock Interrupt controller Timer unit Serial communication interface controller Serial communication interface with IrDA Serial communication interface with FIFO Cache controller Direct memory access controller Analog to Digital converter Digital to Analog converter Port controller User debugging interface Rev. 5.00, 09/03, page 756 of 760 Appendix C Product Lineup Table C.1 Abbr. I/O SH7709S 3.30.3 V Internal 2.00.15 V 1.90.15 V SH7709S Models Power Supply Voltage Operating Frequency 200 MHz 167 MHz Model Marking HD6417709SHF200B HD6417709SF167B HD6417709SBP167B 1.8+0.25 V 1.8-0.15 V 133 MHz HD6417709SF133B HD6417709SBP133B 1.7+0.25 V 1.7-0.15 V 100 MHz HD6417709SF100B HD6417709SBP100B Package 208-pin plastic HQFP (FP-208E) 208-pin plastic LQFP (FP-208C) 240-pin CSP (BP-240A) 208-pin plastic LQFP (FP-208C) 240-pin CSP (BP-240A) 208-pin plastic LQFP (FP-208C) 240-pin CSP (BP-240A) Rev. 5.00, 09/03, page 757 of 760 Appendix D Package Dimensions Figures D.1 to D.3 show the SH7709S package dimensions. Unit: mm 30.0 0.2 28 156 157 105 104 30.0 0.2 208 1 *0.22 0.05 0.20 0.04 52 0.08 M 53 0.5 *0.17 0.05 0.15 0.04 1.70 Max 1.40 1.25 1.0 0 - 8 0.5 0.1 0.08 0.10 0.05 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-208C - Conforms 2.7 g Figure D.1 Package Dimensions (FP-208C) Rev. 5.00, 09/03, page 758 of 760 30.6 0.2 28 156 157 105 104 Unit: mm 30.6 0.2 208 1 *0.22 0.05 0.20 0.04 52 0.10 M 3.56 Max 53 0.5 *0.17 0.05 0.15 0.04 3.20 1.25 1.3 0 - 8 0.5 0.1 0.10 0.15 +0.10 -0.15 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-208E - Conforms 5.3 g Figure D.2 Package Dimensions (FP-208E) Rev. 5.00, 09/03, page 759 of 760 Unit: mm 0.20 C B 0.20 C A 0.65 13.00 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W A 0.65 B 13.00 4x 0.15 0.65 0.65 240 x 0.40 0.05 0.08 M C A B 0.2 C C 0.33 0.05 1.40Max 0.10 C Package Code JEDEC JEITA Mass (reference value) BP-240A - - 0.4 g Figure D.3 Package Dimensions (BP-240A) Rev. 5.00, 09/03, page 760 of 760 SH7709S Group Hardware Manual Publication Date: 1st Edition, September 2001 Rev.5.00, September 18, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. (c)2001, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com Colophon 1.0 SH7709S Group Hardware Manual REJ09B0081-0500O |
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